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参数资料
| 型号： | IDTCSPU877ANLG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 中文描述： | 877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 封装： | GREEN, PLASTIC, MLF-40 |
| 文件页数： | 5/13页 |
| 文件大小： | 139K |
| 代理商： | IDTCSPU877ANLG |
5
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
2. L(z) means the outputs are disabled to a LOW state, meeting the I
ODL
limt in DC Electrical Characteristics table.
3. The device will enter a low power-down mode when CLK and
CLK
are both at logic LOW.
FUNCTION TABLE
(1,2)
INPUTS
OS
X
X
H
OUTPUTS
AV
DD
GND
GND
GND
OE
H
H
L
CLK
L
H
L
CLK
H
L
H
Y
L
H
L(z)
L(z)
Y
7
Active
L(z)
L(z)
Y
7
Active
L
H
L(z)
Y
H
L
L(z)
L(z)
Y
7
Active
L(z)
L(z)
Y
7
Active
H
L
L(z)
FBOUT
L
H
L
FBOUT
H
L
H
PLL
OFF
OFF
OFF
GND
L
L
H
L
H
L
OFF
1.8V (nom
L
H
L
H
L
H
ON
1.8V (nom
L
L
H
L
H
L
ON
1.8V (nom
1.8V (nom
1.8V (nom
X
H
H
X
X
X
X
X
X
L
H
L
H
H
L
L
H
L
H
L(z)
H
L
L(z)
ON
ON
OFF
(3)
(3)
Reserved
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C
Symbol
Parameter
V
IK
Input Clamp Voltage (All Inputs)
V
DDQ
= 1.7V, I
I
= -18mA
V
IL(2)
Input LOW Voltage (OE, OS, CLK,
CLK
)
V
IH(2)
Input HIGH Voltage (OE, OS, CLK,
CLK
)
V
IN(1)
Input Signal Voltage
V
ID(DC)(2)
DC Input Differential Voltage
V
OD(3)
Output Differential Voltage
A
VDD
/V
DDQ
= 1.7V
V
OH
Output HIGH Voltage
I
OH
= -100
μ
A, V
DDQ
= 1.7V to 1.9V
I
OH
= -9mA, V
DDQ
= 1.7V
V
OL
Output LOW Voltage
I
OL
= 100
μ
A, V
DDQ
= 1.7V to 1.9V
I
OL
= 9mA, V
DDQ
= 1.7V
I
ODL
Output Disabled LOW Current
OE = L, V
ODL
= 100mV, A
VDD
/V
DDQ
= 1.7V
I
IN
Input Current CLK,
CLK
A
VDD
/V
DDQ
= Max., V
I
= 0V to V
DDQ
OE, OS, FBIN,
FBIN
I
DDLD
Static Supply Current (I
DDQ
and I
ADD
)
A
VDD
/V
DDQ
= Max., CLK and
CLK
= GND
I
DD
Dynamc Power Supply Current
A
VDD
/V
DDQ
= Max., CLK = 270MHz
(I
DDQ
and I
ADD
)
(4,5)
Conditions
Mn.
0.65V
DDQ
-0.3
0.3
0.5
V
DDQ
- 0.2
1.1
Typ.
Max.
– 1.2
0.35V
DDQ
V
DDQ
+ 0.3
V
DDQ
+ 0.4
0.1
0.6
±250
±10
500
300
Unit
V
V
V
V
V
V
V
100
μ
A
μ
A
μ
A
mA
NOTES:
1. V
IN
specifies the allowable DC excursion of each different output.
2. V
ID
is the magnitude of the difference between the input level on CLK and the input level on
CLK
. The CLK and
CLK
V
IH
and V
IL
limts are used to define the DC LOW and HIGH
levels for the power down mode.
3. V
OD
is the magnitude of the difference between the true output level and the complementary level.
4. All Outputs are left open (unconnected to PCB).
5. Total I
DD
= I
DDQ
+ I
ADD
= F
CK
*C
PD
*V
DDQ
, for Cpd = (I
DDQ
+ I
ADD
) / (F
CK
*V
DDQ
) where F
CK
is the input frequency, V
DDQ
is the power supply, and C
PD
is the Power Dissipation Capacitance.
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