参数资料
型号: IDTQS3B2491TF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 总线收发器
英文描述: 9-BIT EXCHANGER, TRUE OUTPUT, PQFP64
封装: TQFP-64
文件页数: 2/6页
文件大小: 78K
代理商: IDTQS3B2491TF
2
1999 Integrated Device Technology, Inc
IDT
QS3B491 AND QS3B2491
DSC-XXXXXX
In the Asynchronous mode, switch configuration logic behaves as a
Transparent Latch under the control of LE signal. When LE is HIGH, the
Latch is in the transparent mode. When LE is LOW, the configuration
that meets the set-up time requirements is latched. An internal Power-
ON Reset circuir disables all switches during power supply ramp-up and
ramp-down.
Two port selection inputs are provided for port-independent intercon-
nect control. Each port can be independently configured as a source or
destination. This control scheme eliminates ‘illegal’ control input com-
binations.
Each I/O has a programmable Terminator with three modes of operation:
OFF, Active Terminator (Last Value Latch), and Passive (Resistive)
Terminator. Terminators for each port are connected to independent
VBIAS pins (V
BA…VBD)and are controlled by independent Terminator
Control (TCx) pins with three-state inputs. This control arrangement
provides maximum flexibility for voltage translation between ports.
The QS3B491 is a low resistance Crossbar Switch, with ON resistance
of 9
typical. The QS32491 adds an internal series resistor and is ideal for
series termination of PCB traces and for the reduction of signal overshoots
and undershoots.
Control Inputs
Mode
Status
X
L
-
All Switches OFF
X
H
Asynch
Transparent Mode
H
X
L
H
Synch
Hold Previous Configuration
L
L
H
Synch
Load Configuration
L
H
L
H
Asynch
Hold Previous Configuration
L
H
Asynch
Hold Previous Configuration
CLKEN
CLK
LE
OE
CONFIGURATION CONTROL
S1A
S0A
A - Port Status
L
Source
L
H
Destination (B -> A)
H
L
Destination (C -> A)
H
Destination (D -> A)
PORT SELECTION CONTROL
S1D
S0D
D - Port Status
L
Destination (A -> D)
L
H
Destination (B -> D)
H
L
Destination (C -> D)
H
Source
S1C
S0C
C - Port Status
L
Destination (A -> C)
L
H
Destination (B -> C)
H
L
Source
H
Destination (D -> C)
S1B
S0B
B - Port Status
L
Destination (A -> B)
L
H
Source
H
L
Destination (C -> B)
H
Destination (D -> B)
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