参数资料
型号: IDTQS3L388Q
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 总线收发器
英文描述: 5-BIT EXCHANGER, TRUE OUTPUT, PDSO24
封装: QSOP-24
文件页数: 5/6页
文件大小: 111K
代理商: IDTQS3L388Q
5
IDTQS3L388
HIGH-SPEEDCMOSBUSEXCHANGESWITCH
INDUSTRIALTEMPERATURERANGE
IBH
+ 500
Sinking
Current
( + )
IBHL
IBH
IBHH
+60
+20
– 60
– 20
+60 IBHL
0.8V
2V
VIH
– 60 IBHH
V IL
Sourcing
Current
( – )
IBH
– 500
Vcc
+ 20 IBH
– 20 IBH
Voltage
VT
V-I CHARACTERISTICS OF BUS-HOLD CIRCUIT
VT
≡≡≡≡≡ Threshold Voltage ≈ 1.5V
VIL
≈ .8
VIH
≈ 2V
ACTIVE TERMINATOR OR BUS-HOLD CIRCUIT
The Active Terminator circuit, also known as the Bus-hold circuit, is configured as a “weak latch” with positive feedback. When connected to a TTL
or CMOS input port, the Bus-hold circuit holds the last logic state at the input when the input is “disconnected” from the driver. When the output of a device
connected to such an input attempts a logic level transition, it will over-drive the Bus-hold circuit. The primary benefit of this circuit is that it prevents CMOS
inputs from floating, a situation which should be avoided to prevent spurious switching of inputs and unnecessary power dissipation. Bus-hold is a better
solution than the traditional approach of using resistive termination to VCC or GND to prevent bus floating, because the Bus-hold circuit does not consume
any static power.
The figure above shows the input V-I characteristics of a Bus-hold implementation. The input characteristics resemble a resistor. As the input voltage
is increased from 0 volts, the ‘sink’ current increases linearly. When the TTL threshold of the circuit is reached (typically 1 .5 volts), the latch changes the
logic state due to positive feedback and the direction of current is reversed. As the voltage is further increased towards VCC, the input ‘source’ current
begins to decrease, reaching the lowest level at VIN = VCC.
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