参数资料
型号: IDTQS3VH16244PAG8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 总线收发器
英文描述: QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48
封装: TSSOP-48
文件页数: 7/8页
文件大小: 73K
代理商: IDTQS3VH16244PAG8
7
INDUSTRIALTEMPERATURERANGE
IDTQS3VH16244
2.5V / 3.3V 16-BIT HIGH BANDWIDTH BUS SWITCH
Open
VLOAD
GN D
VCC
Pulse
G enerator
D.U.T.
500
CL
RT
VIN
VOUT
(1, 2)
SAM E PH AS E
IN PUT TR AN SITION
OPPOSITE PHASE
IN PU T TRAN SITIO N
0V
VOH
VOL
tPLH
tPHL
tPLH
OU TPUT
VIH
VT
VIH
VT
CONTROL
INPU T
tPLZ
0V
OU TPU T
NORMALLY
LOW
tPZH
0V
SW ITCH
CLO SE D
OU TPU T
NO RM ALLY
HIGH
EN ABLE
D ISABLE
SW ITCH
OPEN
tPHZ
0V
V OL + V LZ
V OH
VT
tPZL
VLOAD/2
VIH
V T
V OL
V OH -V HZ
TEST CIRCUITS AND WAVEFORMS
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Propagation Delay
Test Circuits for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Switch
tPLZ/tPZL
VLOAD
tPHZ/tPZH
GND
tPD
Open
TEST CONDITIONS
Symbol
VCC(1)= 3.3V ± 0.3V
VCC(2)= 2.5V ± 0.2V
Unit
VLOAD
6
2 x Vcc
V
VIH
3
Vcc
V
VT
1.5
VCC/2
V
VLZ
300
150
mV
VHZ
300
150
mV
CL
50
30
pF
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