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参数资料
| 型号： | IDTQS53805SO |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 1/6页 |
| 文件大小： | 96K |
| 代理商： | IDTQS53805SO |
1
QS53805/A
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIALTEMPERATURERANGE
JULY 2000
1999
Integrated Device Technology, Inc.
DSC-5842/-
c
QS53805/A
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
3.3V CMOS CLOCK
DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
OE A
IN A
IN B
OA 5
OA 1
5
MON
OB 5
OB 1
OE B
DESCRIPTION
The QS53805 clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of 5 non-inverting outputs. The QS53805 device provides low propagation
delay buffering with on-chip skew of 0.7ns for same-transition, same-bank
signals. This clock buffer product is designed for use in high performance
workstations, embedded and personal computing systems using 3V to 3.6V
supply voltages. Several can be used in parallel or scattered throughout
a system for guaranteed low skew, system-wide clock distribution net-
works. The QS53805 can accept 5V input and control signals.
The QS53805 is characterized for operation at -40°C to +85°C.
FEATURES:
10 output, low skew clock signal buffer
Pinout and function compatible with QS5805T
JEDEC compatible LVTTL inputs and outputs
Input hysteresis for better noise margin
Monitor output
Guaranteed low skew:
0.7ns output skew
1.1ns pulse skew
1ns part-to-part skew
Clock inputs are 5V tolerant
Std. and A speed grades
Available in QSOP and SOIC packages
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