参数资料
型号: IL262-3E
厂商: NVE Corp/Isolation Products
文件页数: 6/16页
文件大小: 0K
描述: ISOLATOR HS 5CHAN DIGITAL 16SOIC
产品培训模块: IsoLoop® Isolator
产品目录绘图: IL262 Circuit
标准包装: 50
系列: IsoLoop®
输入 - 1 侧/2 侧: 3/2
通道数: 5
电源电压: 3 V ~ 5.5 V
电压 - 隔离: 2500Vrms
数据速率: 110Mbps
传输延迟: 12ns
输出类型: CMOS
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC N
包装: 管件
工作温度: -40°C ~ 85°C
产品目录页面: 2771 (CN2011-ZH PDF)
其它名称: 390-1116-5
IL260/IL261/IL262
5 Volt Electrical Specifications (T min to T max )
Parameters
Symbol Min. Typ. Max.
Units
Test Conditions
IL260
350
500
μ A
Input Quiescent Current
Output Quiescent Current
IL261
IL262
IL260
IL261
IL262
I DD1
I DD2
1.8
3.6
9
7.2
7.2
2.5
5
12.5
10
10
mA
mA
mA
mA
mA
Logic Input Current
I i
? 10 10
μ A
Logic High Output Voltage
Logic Low Output Voltage
V OH
V OL
V DD ? 0.1 V DD
0.8 x V DD 0.9 x V DD
0 0.1
0.5 0.8
V
V
I O = ? 20 μ A, V I = V IH
I O = ? 4 mA, V I = V IH
I O = 20 μ A, V I = V IL
I O = 4 mA, V I = V IL
Switching Specifications (V DD = 5 V)
Maximum Data Rate
Minimum Pulse Width (7)
PW
100 110
10
Mbps
ns
C L = 15 pF
50% Points, V O
Propagation Delay Input to Output
(High to Low)
Propagation Delay Input to Output
(Low to High)
Pulse Width Distortion |t PHL ? t PLH | (2)
Pulse Jitter (10)
Propagation Delay Skew (3)
Output Rise Time (10%–90%)
Output Fall Time (10%–90%)
t PHL
t PLH
PWD
t J
t PSK
t R
t F
10
10
2
100
4
1
1
15
15
3
6
3
3
ns
ns
ns
ps
ns
ns
ns
C L = 15 pF
C L = 15 pF
C L = 15 pF
C L = 15 pF
C L = 15 pF
C L = 15 pF
C L = 15 pF
Common Mode Transient Immunity
(Output Logic High to Logic Low) (4)
Channel-to-Channel Skew
Dynamic Power Consumption (6)
|CM H |,|CM L |
30
50
2
200
3
340
kV/ μ s
ns
μ A/Mbps
V CM = 1500 V DC
t TRANSIENT = 25 ns
C L = 15 pF
per channel
Magnetic Field Immunity (8) (V DD2 = 5V, 3V<V DD1 <5.5V)
Power Frequency Magnetic Immunity
Pulse Magnetic Field Immunity
Damped Oscillatory Magnetic Field
Cross-axis Immunity Multiplier (9)
H PF
H PM
H OSC
K X
2800 3500
4000 4500
4000 4500
2.5
A/m
A/m
A/m
50Hz/60Hz
t p = 8μs
0.1Hz – 1MHz
Notes (apply to both 3.3 V and 5 V specifications):
1.
2.
3.
4.
5.
6.
7.
8.
9.
Absolute maximum means the device will not be damaged if operated under these conditions. It does not guarantee performance.
PWD is defined as |t PHL ? t PLH |. %PWD is equal to PWD divided by pulse width.
t PSK is the magnitude of the worst-case difference in t PHL and/or t PLH between devices at 25°C.
CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD 2 . CM L is the maximum
common mode input voltage that can be sustained while maintaining V O < 0.8 V. The common mode voltage slew rates apply to both rising
and falling common mode voltage edges.
Device is considered a two terminal device: pins 1–8 shorted and pins 9–16 shorted.
Dynamic power consumption numbers are calculated per channel and are supplied by the channel’s input side power supply.
Minimum pulse width is the minimum value at which specified PWD is guaranteed.
The relevant test and measurement methods are given in the Electromagnetic Compatibility section on p. 6.
External magnetic field immunity is improved by this factor if the field direction is “end-to-end” rather than to “pin-to-pin” (see diagram on p. 6).
10. 66,535-bit pseudo-random binary signal (PRBS) NRZ bit pattern with no more than five consecutive 1s or 0s; 800 ps transition time.
6
NVE Corporation
11409 Valley View Road, Eden Prairie, MN 55344-3617
Phone: (952) 829-9217
Fax: (952) 829-9189
www.IsoLoop.com
?NVE Corporation
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