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参数资料
| 型号： | IM8R-67025V-45 |
| 厂商： | TEMIC SEMICONDUCTORS |
| 元件分类： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 45 ns, CPGA84 |
| 封装： | PGA-84 |
| 文件页数： | 20/23页 |
| 文件大小： | 257K |
| 代理商： | IM8R-67025V-45 |
M 67025
MATRA MHS
Rev. D (29/09/95)
6
The dual-port RAM has a fast access time, and the two
ports are completely independent of each another. This
means that the activity on the left port cannot slow the
access time of the right port. The ports are identical in
function to standard CMOS static RAMs and can be read
from, or written to, at the same time with the only possible
conflict arising from simultaneous writing to, or a
simultaneous
READ/WRITE
operation
on,
a
non-semaphore location. Semaphores are protected
against such ambiguous situations and may be used by the
system
program
to
prevent
conflicts
in
the
non-semaphore segment of the dual-port RAM. The
devices
have
an
automatic
power-down
feature
controlled by CS, the dual-port RAM select and SEM, the
semaphore enable. The CS and SEM pins control
on-chip-power-down circuitry that permits the port
concerned to go into stand-by mode when not selected.
This conditions is shown in table 1 where CS and SEM
are both high.
Systems best able to exploit the M 67025 are based
around multiple processors or controllers and are
typically
very
high-speed,
software
controlled
or
software-intensive systems. These systems can benefit
from the performance enhancement offered by the
M 67025 hardware semaphores, which provide a lock-out
mechanism without the need for complex programming.
Software handshaking between processors offers the
maximum level of system flexibility by permitting shared
resources to be allocated in varying configurations. The
M 67025 does not use its semaphore flags to control any
resources through hardware, thus allowing the system
designer total flexibility in system architecture.
An advantage of using semaphores rather than the more
usual methods of hardware arbitration is that neither
processor ever incurs wait states. This can prove to be a
considerable advantage in very high speed systems.
How The Semaphore Flags Work
The semaphore logic is a set of eight latches independent
of the dual-port RAM. These latches can be used to pass
a flag or token, from one port to the other to indicate that
a shared resource is in use. The semaphore provide the
hardware context for the “Token Passing Allocation”
method of use assignment. This method uses the state of
a semaphore latch as a token indicating that a shared
resource is in use. If the left processor needs to use a
resource, it requests the token by setting the latch. The
processor then verifies that the latch has been set by
reading it. If the latch has been set the processor assumes
control over the shared resource. If the latch has not been
set, the left processor has established that the right
processor had set the latch first, has the token and is using
the shared resource. The left processor may then either
repeatedly query the status of the semaphore, or abandon
its request for the token and perform another operation
whilst occasionally attempting to gain control of the
token through a set and test operation. Once the right side
has relinquished the token the left side will be able to take
control of the shared resource.
The semaphore flags are active low. A token is requested
by writing a zero to a semaphore latch, and is relinquished
again when the same side writes a one to the latch.
The eight semaphore flags are located in a separate
memory space from the dual-port RAM in the M 67025.
The address space is accessed by placing a low input on
the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins
(address, OE and R/W) as normally used in accessing a
standard static RAM. Each of the flags has a unique
address accessed by either side through address pins
A0-A2. None of the other address pins has any effect
when accessing the semaphores. Only data pin D0 is used
when writing to a semaphore. If a low level is written to
an unused semaphore location, the flag will be set to zero
on that side and to one on the other side (see table 5). The
semaphore can now only be modified by the side showing
the zero. Once a one is writen to this location from the
same side, the flag will be set to one for both sides (unless
a request is pending from the other side) and the
semaphore can then be written to by either side.
The effect the side writing a zero to a semaphore location
has of locking out the other side is the reason for the use
of semaphore logic in interprocessor communication. (A
thorough discussion of the use of this feature follows
below). A zero written to the semaphore location from the
locked-out side will be stored in the semaphore request
latch for that side until the semaphore is relinquished by
the side having control. When a semaphore flag is read its
value is distributed to all data bits so that a flag set at one
reads as one in all data bits and a flag set at zero reads as
all zeros. The read value is latched into the output register
of one side when its semaphore select (SEM) and output
enable (OE) signals go active. This prevents the
semaphore changing state in the middle of a read cycle as
a result of a write issued by the other side. Because of this
latch, a repeated read of a semaphore flag in a test loop
must cause either signal (SEM or OE) to go inactive,
otherwise the output will never change.
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