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参数资料
| 型号： | IMIC9806IAT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | TSSOP-48 |
| 文件页数： | 10/14页 |
| 文件大小： | 221K |
| 代理商： | IMIC9806IAT |
C9806I
I
2C Frequency Clock Generator for Mobile Pentium II Applications.
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.0
4/25/2000
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 5 of 14
http://www.imicorp.com
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
Byte 0: Function Select Register
Bit
@Pup
Pin#
Description
70
*
Reserved
61
*
SST2* (see table5, p.7)
51
*
SST1* (see table5, p.7)
41
*
SST0* (see table5, p.7)
3
1
22
24/48M, 1 selects 48mhz, 0 selects 24MHz.
2
1
23
24/48M, 1 selects 48mhz, 0 selects 24MHz.
1
0
Bit1 Bit0
1
1 Tri-State (all outputs)
1
0 Spread Spectrum enabled
0
1 Test Mode
0
NON spread spectrum operating mode
Byte 1: CPU, AGP, 48/24 MHz Register (1 = Enable, 0
= Stopped)
Bit
@Pup
Pin#
Description
7
1
22
48/24 MHz Enable/Stopped
6
1
23
48/24 MHz Enable/Stopped
5
x
-
Reserved
4
x
-
Reserved
3
1
38
SDRAM_FB Enable/Stopped
2
1
39
If programmed to 0, CPU0
will be independent of
CPU_STP# condition
1
41
CPU1 Enable/Stopped
0
1
42
CPU0 Enable/Stopped
Byte 2: PCI Register (1 = Enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7x
-
Reserved
6
1
8
PCICLK_F Enable/Stopped
5
1
16
PCICLK5 Enable/Stopped
4
1
14
PCICLK4 Enable/Stopped
3
1
13
PCICLK3 Enable/Stopped
2
1
12
PCICLK2 Enable/Stopped
1
11
PCICLK1 Enable/Stopped
0
1
9
PCICLK0 Enable/Stopped
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