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参数资料
| 型号： | IMISC462AYB |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 0.209 INCH, SSOP-28 |
| 文件页数： | 1/7页 |
| 文件大小： | 61K |
| 代理商： | IMISC462AYB |
SC462
Green PC Power Management Clock Generator
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.0
8/15/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 1 of 7
PRODUCT FEATURES
Generates all essential clock signals for the
motherboards
4V to 7V operating supply range
Supports 8086, 80286, 80386 and 80486 including
S Series and Pentium based designs
Integrates keyboard clock, CPU clock and buffered
14.318 Mhz output
Wide range of
selectable output
frequencies
including 100, 80, 66.6, 60, 50, 40, 33.3, 16, 8 and
2 Mhz
Power down mode for low power consumption
Selectable DOZE mode
RESUME# output for S Series type processor
compatability
Single, low cost crystal (14.318 Mhz) used as
reference frequency
Smooth and glitch-free switching for programmable
clock generator
50% duty cycle
TTL or CMOS compatible outputs
Low, short and long term jitter
28 PDIP and 28 Pin SSOP (209 mil body) package
options
BLOCK DIAGRAM
PRODUCT DESCRIPTION
The IMISC462 is a clock chip for motherboards. The
IMISC462 includes two independent VCO’s and uses a
single 14.318 Mhz external crystal to generate all
essential clock signals. The IMISC462 is designed to
generate CPU clock optionsof 100 Mhz, 80 Mhz, 66.6
Mhz, 60 Mhz, 50 Mhz, 40 Mhz, 33.3 Mhz, 16 Mhz, 8
Mhz and 2 Mhz, as well as the resultant frequencies
from dividing these frequencies by 2, giving flexibility
to the user. The frequency selection on the MCLK
outputs id determined by the S0-S2 pins. A second
fixed frequency clock generator provides 24 Mhz and 8
Mhz. In addition, the REF14 output provides a buffered
(14.318 Mhz) output. DOZE# and RESUME# pins give
additional
flexibility
to
the
user
for
Green
PC
applications.
Activating
the
DOZE
pin
smoothly
switches the MCLK outputs down to DOZE frequencies
selected by ST0-ST1 inputs. Deactivating the DOZE
input allows the CPU outputs to return to full speed and
causes the RESUME# output to go high after the
MCLK outputs have become stable at full speed for 1
millisecond.
All VCO’s can be turned off in the tri-state mode,
reducing the current consumption to a few milliamps.
CONNECTION DIAGRAM
REF
CLOCK
GEN 1
CLOCK
GEN 2
14.318 MHz
REF14
DOZE#
LF1
S0
MCLK2
S1
MCLK1
ST0
S2
RESUME#
ST1
TS#
LF2#
24 MHz
8 MHz
Bout1
Bin
Bout2
Bout3
Bout4
OSCin
1
REF14
28
OSCout
2
RESUME#
3
S0
4
S1
5
S2
6
AVDD
7
LF1
8
AVSS
9
LF2
10
VSS
11
MCLK1
12
ST1
13
ST0
14
Bout4
27
DOZE#
26
VDD
25
Bout3
24
24 MHz
23
VSS
22
MCLK2
21
TS#
20
Bout2
19
Bout1
18
VDD
17
Bin
16
8 MHz
15
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