
SC464
Motherboard Clock Chip
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev. 1.1
5/22/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 8
OSCin, OSCout
- These pins form
an on-chip
reference oscillator when connected to terminals of an
external parallel resonant crystal (nominally 14.318
MHz).
OSCin may also serve as an input for an
externally generated reference signal.
S0, S1, and S2 - Standard frequency select inputs.
These inputs control the high speed MCLK frequency
selection.
S0-S2
inputs
control
the
CPU
clock
frequencies. All these inputs have internal pull-ups.
Frequency table shows the output frequency selection
conditions.
MCLK1 and MCLK2 - Synchronous master clock
outputs.
Programmable output frequencies can be
selected using S0 - S2 inputs shown in Frequency table.
DOZE# - Doze control pin. When DOZE# is high, the
clock chip operates in the standard mode. When this
pin goes low, MCLK1 and MCLK2 frequencies are
switched to the pre-programmed DOZE frequencies.
Switching to DOZE frequencies occur smoothly to allow
tracking by 486 CPU internal PLL. This pin has an
internal pull-up.
REF14 - 14.31818 MHz output. Buffered output of on-
chip
reference
oscillator
or
externally
provided
reference.
LF1 - This is the phase detector output for the clock
generator. It is a single-ended, tri-state output for use as
a loop error signal. A 1uF capacitor to ground should
be connected from this pin to form the loop filter.
VSS - Circuit Ground
VDD - Positive power supply.
AVSS - Analog circuit ground
AVDD - Analog positive power supply.
ST # - When this pin is active low, MCLK20 stops after
1.1ms. When this pin is deactive, MCLK20 starts up
immediately.
RESUME # - When ST# pin is active low, Resume# pin
goes to zero immediately. When ST# pin is deactive,
Resume# in goes to high after 1.1ms.
MAXIMUM RATINGS
Input Voltage Relative to VSS:
-0.3V to 7V
Input Voltage Relative to VDD:
0.3V
Storage Temperature:
-65C to 150C
Ambient Temperature:
0C to 70C
Recommend Operating Range:
4.5 - 5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate
logic voltage level (ever VSS or VDD).