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参数资料
| 型号： | IMISC612CYB |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO34 |
| 封装： | SSOP-34 |
| 文件页数： | 2/5页 |
| 文件大小： | 82K |
| 代理商： | IMISC612CYB |
SC612
Low Cost Clock Generator for VX with 1 SDRAM Bank
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.1
4/24/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 5
PIN DESCRIPTION
Xin, Xout - These pins form an on-chip reference
oscillator when connected to terminals of an external
parallel resonant crystal (nominally 14.318 MHz). Xin
may also serve as input for an externally generated
reference signal.
S0, S1, and S2 - Standard frequency select inputs.
These inputs have internal pull-ups.
CPU(1:4) - Low skew (<250 pS) clock outputs for host
frequencies such as CPU, Chipset, Cache, etc.. CPU
clock output voltage level is controlled by B1VDD.
Buffers have 60 mA switching current at 3.3V.
SDRM(1:4) - Low skew (<250 pS) clock outputs for
SDRAM modules voltage level is controlled by B2VDD.
Buffers have 120 mA switching current at 3.3V.
PCI(1:6) - Low skew (<250pS) clock outputs for PCI
frequencies.
These buffers voltage level is controlled
by VDD. These outputs have 60 mA switching current at
3.3V.
REF1, REF2 - Buffered output of on-chip reference.
Outputs have 60mA switching current at 3.3V.
48MHz - Frequency output for USB.
24MHz - Frequency output for Floppy Drive.
F.A.S.T.# - When this input is pulled low, the frequency
of the CPU clock and PCI clock (in synchronous mode
only) is increased by the specified percentage (see
table, page 1). This input has an internal pull-up.
VSS - Circuit Digital ground.
VDD - Circuit digital positive power supply.
B1VDD - 3.3V/5V logic level control for CPU(1:4)
outputs. Voltage cannot be greater than VDD.
B2VDD - 3.3V/5V logic level control for SDRAM (1:4)
outputs. Voltage cannot be greater than VDD.
MAXIMUM RATINGS
Voltage Relative to VSS:
-0.3V
Voltage Relative to VDD:
0.3V
Storage Temperature:
-65C to + 150C
Ambient Temperature:
-55C to +125C
Maximum Power Supply:
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
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