参数资料
型号: IMISC662AAB
元件分类: 时钟产生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PQFP52
封装: QFP-52
文件页数: 2/5页
文件大小: 147K
代理商: IMISC662AAB
SC662
Clock Generator for Power PC Designs with SDRAM and USB Support
Preliminary Product Information
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.1
4/11/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 5
PIN DESCRIPTION
Xin, Xout - These pins form an on-chip reference
oscillator when connected to terminals of an external
parallel resonant crystal (nominally 14.318 MHz). Xin
may also serve as input for an externally generated
reference signal.
Sel0, Sel1, and Sel2 - Standard frequency select
inputs. These inputs have internal pull-ups.
CPU(1:4) - Low skew (<250 pS) clock outputs for host
frequencies such as CPU, Chipset, Cache, etc... CPU1-
CPU4 voltage level is controlled by VDDCPU. CPU
buffers have 60 mA switching current at 3.3V.
SDRM(1:12) - Low skew (<250 pS) clock outputs for
SDRAM. Voltage level is controlled by VDDRM. SDRM
buffers have 60 mA switching current at 3.3V.
IOAPIC - Buffered output clock of the crystal.
This
buffer has 60 mA switching current at 3.3V. Voltage
level is controlled by VDDIO.
PCI(1:8) - Low skew (<250pS) clock outputs for PCI
frequencies.
This buffer voltage level is controlled by
VDD. All these outputs have 60 mA switching current at
3.3V.
REF(1:2) - Buffered output of on-chip reference.
Outputs have 60mA switching current at 3.3V.
48MHz - Frequency output for USB.
VSS - Circuit ground.
VDD - Positive power supply.
VDDCPU - 3.3V/2.5V logic level control for CPU(1:4)
outputs. Voltage cannot be greater than VDD.
VDDRM - 3.3V/2.5V logic level control for SDRM(1:12)
outputs. Voltage cannot be greater than VDD.
VDDIO - 3.3V/2.5V logic level control for IOAPIC output.
Voltage cannot be greater than VDD.
MAXIMUM RATINGS
Voltage Relative to VSS:
-0.3V
Voltage Relative to VDD:
0.3V
Storage Temperature:
-65C to + 150C
Ambient Temperature:
-55C to +125C
Maximum Power Supply:
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
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