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参数资料
| 型号： | IMISC693DXB |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 2/5页 |
| 文件大小： | 77K |
| 代理商： | IMISC693DXB |
SC693
Clock Generator for Pentium and 6X86 Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.4
4/23/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 5
PIN DESCRIPTIONS
Xin and Xout- These pins form an on-chip reference
oscillator when connected to terminals of an external
parallel resonant crystal of 14.31818 at 22 PF load. Xin
may also serve as an input for an externally generated
CMOS reference signal.
PCLK(1:4) - Low skew (<250pS) buffered outputs for
host clocks.
These outputs have 60mA switching
currents at 3.3v.
BCLK(1:6) - Low skew (<250pS) buffered outputs for
PCI clocks.
These outputs have 60mA switching
currents at 3.3v. They are synchronous and 2 nS (Typ)
offset to PCLK.
48 MHz - 48 MHz USB clock output
24 MHz - 24 MHz Floppy drive clock output
REF0, REF1 - 14.31818 MHz clock outputs.
S2, S1 and S0- Frequency select inputs. These inputs
select the frequency of the PCLK and BCLK outputs. All
have internal pull-ups.
VSS - Circuit grounds.
VDD- Positive power supplies. May be 5.0 or 3.3 volt.
VDDP - Positive Power supply for PCLK(1:4) - Buffers
may be 5.0, 3.3 or 2.5 volts.
A bypass capacitor (0.1
F) should be placed as
close as possible to each VDD pin. If these bypass
capacitors are not close to the pins their high
frequency filtering characteristic will be cancelled
by the lead inductances of the traces.
MAXIMUM RATINGS
Voltage Relative to VSS
-0.3V
Voltage Relative to VDD
0.3V
Storage Temperature:
-65
°C to +150°C
Ambient Temperature:
-0
°C to + 70°C
Maximum Supply Voltage
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)< VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
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