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参数资料
| 型号： | IMISG522BX |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 120 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.300 INCH, PLASTIC, SOIC-16 |
| 文件页数： | 8/12页 |
| 文件大小： | 122K |
| 代理商： | IMISG522BX |
SG521/22/24/28
Spread Spectrum Clock Generator
Approved Product
INTERNATIONAL MICROCIRCUITS,INC. 525 LOS COCHES ST.,
Rev. 2.0
5/25/2000
MILPITAS, CA 95035 408-263-6300, FAX 408-263-6571
Page 5 of 12
http:/www.imicorp.com
Test Conditions: VDD=3.3/5.0 V (+/-10%) , CL=15pF and TA=0 to 70
°C unless otherwise specified
Timing Electrical Characteristics
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Conditions
Find
Reference Frequency, delta
-10
+10
%
OSCin = 14.318, 44.24 and 48 MHz
Fout
Frequency, Output
10
-
120
MHz
PRCLK
Tr
Rise Time, PRCLK,
250
-
500
ps
Measured at 0.4 – 2.4V, @50.00 MHz
Tf
Fall Time, PRCLK
200
-
300
ps
Measured at 0.4 – 2.4V, @50.00 MHz
Tr
Rise Time, MPCLK
450
-
650
ps
Measured at 0.4 – 2.4V, @50.00 MHz
Tf
Fall Time, MPCLK
300
-
400
ps
Measured at 0.4 – 2.4V, @50.00 MHz
PRdty
Duty Cycle, PRCLK
45
50
55
%
Measured at 1.5 Volts
MPdty
Duty Cycle, MPCLK
45
50
55
%
Measured at 1.5 Volts
PRccj
Jitter, Cycle to Cycle, PRCLK
-
205
235
ps
3.30 VDC @ 50 MHz, Mod Off
PRccj
Jitter, Cycle to Cycle, PRCLK
-
215
250
ps
3.30 VDC @ 50 MHz, Mod On
PRccj
Jitter, Cycle to Cycle, PRCLK
-
216
250
ps
3.30 VDC @ 40 MHz, Mod Off
PRccj
Jitter, Cycle to Cycle, PRCLK
-
281
325
ps
3.30 VDC @ 40 MHz, Mod On
PRccj
Jitter, Cycle to Cycle, PRCLK
-
320
375
ps
5.0 VDC @ 50 MHz, Mod Off
PRccj
Jitter, Cycle to Cycle, PRCLK
-
324
375
ps
5.0 VDC @ 50 MHz, Mod On
PRccj
Jitter, Cycle to Cycle, PRCLK
-
191
225
ps
5.0 VDC @ 40 MHz, Mod Off
PRccj
Jitter, Cycle, to Cycle, PRCLK
-
351
400
ps
5.0 VDC @ 40 MHz, Mod On
Crystal Selection Truth Table
The SG521, 2, 4 and 8 uses one of three different reference frequencies. Determine the desired PRCLK frequency
from the frequency selection tables in table 5 – 8.
Determine the REQUIRED REFERENCE FREQUENCY,
MPCLK and Product from table 1 and set S2, S3 and S4 control lines as indicated. Note that MPCLK/S3 and
PRCLK/S2 are bi-directional signals and serve as an input control line during power up and an output after power is
stable.
PRODUCT
REQUIRED
REF. Input
(MHz)
MPCLK OUT
(MHz)
(Pin 14)
S4
(Pin 5)
MPCLK/S3
(Pin 14)
PRCLK/S2
(Pin 12)
SG528
44.240
3.7 (44.24/12)
0
SG521/22/24
48.000
0
SG521/22/24/28
14.318
48.000
0
1
SG521/22/24/28
48.000
0
1
0
SG521/22/24/28
44.240
3.7 (44.24/12)
0
1
SG528
44.240
11.6 (44.24/4)
1
0
SG521/22/24
14.318
48.000
1
0
SG521/22/24/28
14.318
48.000
1
0
1
SG521/22/24/28
48.000
1
0
SG521/22/24/28
44.240
11.6 (44.24/4)
1
Table. 1
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