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参数资料
| 型号： | IMISG524BX |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 120 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.300 INCH, PLASTIC, SOIC-16 |
| 文件页数： | 2/12页 |
| 文件大小： | 122K |
| 代理商： | IMISG524BX |
SG521/22/24/28
Spread Spectrum Clock Generator
Approved Product
INTERNATIONAL MICROCIRCUITS,INC. 525 LOS COCHES ST.,
Rev. 2.0
5/25/2000
MILPITAS, CA 95035 408-263-6300, FAX 408-263-6571
Page 10 of 12
http:/www.imicorp.com
SG521 Application Schematic
Figure 2.
Application Schematic Notes:
The application schematic shown in figure 2 above is a typical wiring diagram of the SG521. As depicted in this
schematic, the SG521 will produce 48.00 MHz on the MPCLK output and a modulated 50.00 MHz on the PRCLK
output. Pin 10 controls the amount of modulation on PRCLK, pin 12. When SS-SEL is high, modulation is 3.25%
total spread and when SS-SEL is low, the total modulation is 1.25%.
Other considerations for this circuit is to insure that the power supply bypass capacitors, C2 and C3, are placed as
closed to their respective pins as possible. Also, be sure that the oscillator components, X1, C4 and C5, are placed
as close to pins 2 and 3 as possible.
Certain applications may require a separate island on the PCB for Power and Ground circuits for the SG521. This
is not a requirement, but will improve the immunity, which can directly effect the Phase detector and VCO within the
SG521.
VCC
* * *
VDD(High) = 3.25% Down Spread (Default)
VSS(Low ) = 1.25% Down Spread
* * * SS-SEL
48.00 MHz
Non-modulated
50.00 MHz
Modulated
Y1
14.318 MHz
C4
27pF.
C5
27 pF.
R2
33
R5
33
R4
1.2 K
R3
1.2 K
U1
SG521
V
D
1
6
15
PRCLK/S2
12
MPCLK/S3
14
S0
7
S1
8
S4
5
V
S
4
V
S
11
13
OSCin
2
OSCout
3
SSON
9
SS-SEL
10
T
E
S
T
16
C1
0.1 uF
C2
0.1 uF
C3
0.1 uF
MPCLK
PRCLK
V
S
V
D
V
D
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