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参数资料
| 型号： | IMISG570CYB |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 10/14页 |
| 文件大小： | 176K |
| 代理商： | IMISG570CYB |
SG570
I
2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.1
3/23/98
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 5 of 14
SERIAL CONTROL REGISTERS (Cont.)
Function Table
Function
Outputs
Description
CPU
PCI
SDRAM
Ref
IOAPIC
24MHZ
48MHZ
Tri-State
Hi-Z
Test Mode
Tclk/2
Tclk/4
Tclk/2
Tclk
Tclk/4
Tclk/2
Normal SEL=1
66
CPU/2
CPU
14.318
24
48
Normal SEL=0
60
CPU/2
CPU
14.318
24
48
Notes:
1. Tclk is a test clock over driven on the Xin input during test mode.
2. The frequency ratio Fout/Fin for the USB output is 3.35294.
Byte 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
1
23
48/24 MHz enable/Stopped
6
1
22
48/24 MHz enable/Stopped
5
x
-
Reserved
4
x
-
Reserved
3
1
38
CPUCLK3 enable/Stopped
2
1
39
CPUCLK2 enable/Stopped
1
41
CPUCLK1 enable/Stopped
0
1
42
CPUCLK0 enable/Stopped
Byte 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7x
-
Reserved
6
1
8
PCICLK_F enable/Stopped
5
1
16
PCICLK5 enable/Stopped
4
1
14
PCICLK4 enable/Stopped
3
1
13
PCICLK3 enable/Stopped
2
1
12
PCICLK2 enable/Stopped
1
11
PCICLK1 enable/Stopped
0
1
9
PCICLK0 enable/Stopped
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