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参数资料
| 型号： | IMISM532AXB |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | SOIC-16 |
| 文件页数： | 2/14页 |
| 文件大小： | 132K |
| 代理商： | IMISM532AXB |
+/+
YJGP VKOKPI KU ETKVKECN
SM532
Approved Product
Low EMI Sprectum Spread Clock
International Microcircuits,Inc.
8/31/98
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
Rev. 1.4
http:/www.imicorp.com
Page 10 of 14
Figure 7 shows the clock from figure 6, as displayed on an oscilloscope. Modulation can be seen as the rising and
falling edges of the clock moving back and forth in time.
Figure 7. Period Comparison Chart
There are certain cases where center spread modulation is not applicable. If the maximum design frequency of
the intended application is 50 MHz and becomes unstable above 50 MHz, then increasing the clock to 50.625 MHz
might cause unwanted system problems. To accommodate this situation, it is recommended that the SM530 be
used in the Down Spread mode.
Referring to figure 6, you will note that the peak amplitude of the 50 MHz non-modulated clock is higher than the
wideband modulated clock. This difference in peak amplitudes between modulated and unmodulated clocks is the
reason why SSCG clocks are so effective in digital systems. The illustration in figure 6 refers to the fundamental
clock frequency. A very important characteristic of the SSCG clock is that the bandwidth of the harmonics is
multiplied by the harmonic number. In other words, if the bandwidth of a 50 MHz clock is 1.35 MHz, the bandwidth
of the 3
rd harmonic will be 3 times 1.35, or 4.05 MHz. The amount of bandwidth is relative to the amount of peak
energy in the clock. Consequently, the wider the bandwidth, the greater the energy reduction of the clock. Most
applications will not have a problem meeting agency specifications at the fundamental frequency. It is the higher
harmonics that usually cause the most problems. With an SSCG clock, the bandwidth and peak energy reduction
increases with the harmonic number. Consider that the 11
th harmonic of our 50 MHz clock is 550 MHz. With a
total spread of 1.35 MHz at 50 MHz, the spread at the 11
th harmonic would be 14.85 MHz which greatly reduces
the peak energy content. It is typical to see as much as 12 or 18 dB. of reduction at the higher harmonics, due to
a modulated clock.Referring to figure 6, you can see that the peak amplitude of the non-modulated clock is much
higher than the peak amplitude of the modulated clock. This is the reason the SM532 is used for EMI reduction.
The amount of EMI reduction is dependent on the application. The difference in the peak energy of the modulated
clock and the non-modulated clock in typical applications will see a 2 - 3 dB. reduction at the fundamental and as
much as 8 - 10 dB. reduction at the intermediate harmonics, 3
rd, 5th, 7th etc. At the higher harmonics, it is quite
possible to reduce the peak harmonic energy, compared to the unmodulated clock, by as much as 12 - 18 dB.
The dB reduction for a give frequency and spread can be calculated using a simple formula. This formula is only
helpful in determining a relative dB reduction for a given application. This formula assumes an ideal clock with
50% duty cycle and therfore only predicts the EMI reduction of even harmonics. Other circumstances such as
non-ideal clock and noise will affect the actual dB reduction. The formula is as follows;
dB = 6.5 + 9(Log10(F)) + 9(Log10(P))
Where; F = Frequency in Mhz, P = total % spread (2.5% = .025)
Using a 50 Mhz clock with a 2.5% spread, the theoretical dB reduction would be;
db @ 50 MHz (Fund) = 6.5 + 15.29 - 14.42 = 7.37
dB @ 150 MHz (3rd) = 6.5 + 19.58 - 14.42 = 11.66
dB @ 550 MHz (11th) = 6.5 + 24.66 - 14.42 = 16.74
Tc = 20.202 ns.
Tc = 19.75 ns.
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相关代理商/技术参数 |
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|---|---|
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| IMISM560BZ | 制造商:Cypress Semiconductor 功能描述:PLL Frequency Synthesizer Single 25MHz to 108MHz 8-Pin SOIC 制造商:Rochester Electronics LLC 功能描述:TIMING DEVICE - Bulk |
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