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参数资料
| 型号： | IMIZ9104DAB |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32 |
| 文件页数： | 5/7页 |
| 文件大小： | 120K |
| 代理商： | IMIZ9104DAB |
Z9104
Document #: 38-07083 Rev. *C
Page 5 of 7
Notes:
7.
Parameters are guaranteed by design and characterization. Not 100% tested in production.
8.
Outputs are loaded with 33 pF each.
9.
REFIN rise time = FBIN rise time.
10. Tpd measurement uses the averaging feature of the scope to filter out the jitter component.
AC Parameters[7]: VDD = VDDF = 3.3V±5%, VDD25 = 2.5V±5%, TA = –40°C to +85°C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Tr,Tf
REFIN Rise/Fall Time
0.4 to 2.4 Volts
3.0
ns
FVCO
VCO lock range
200
480
MHz
Fmax
Maximum output frequency
Pcounter = 4
120
MHz
REFIN
Input Reference Frequency
See Table 2
Controlled by VCO lock
range
MHz
FrefDC
Reference Input Duty Cycle
Measured @ 1.5V
25
75
%
TSkewO
Output to Output clock skew
(CLK(2:6])[8]
Measured at 1.5 Volts
300
ps
TSkewO25
Output to Output clock skew (CLK25
to Q(2:6))[8]
Measured at 1.5 V on CLK(2:6) and at
1.25V on CLK25
600
ps
Tpd
REFIN to FBIN Average Delay[9,10] Fin = 66.6 MHz
–150
0
+150
ps
DC
Output Duty Cycle
Measured at 1.5 V on CLK(2:6) and at
1.25V on CLK25
45
50
55
%
Tr,Tf
Output Rise/Fall Time
Measured from 0.8V to 2.0V on CLK(2:6)
and from 0.8V to 1.8V on CLK25
0.1
1.2
ns
Ten
Output Enable Time
2.0
10
ns
Tdis
Output Disable Time
2.0
8.0
ns
Tjitter
Cycle-to-cycle jitter
Short term jitter (adjacent cycle) Select
Code 100 50 MHz in/out
+100
ps
Tlock
Maximum PLL Lock Time
10
ms
Tpr
Power Up Ramp Time
Measured between 0.3V and 3.0V
250
20 ms
ns
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