参数资料
型号: IN74AC573DW
厂商: INTEGRAL JOINT STOCK COMPANY
英文描述: Octal 3-State Noninverting Transparent Latch
中文描述: 八路三态同相透明锁存器
文件页数: 4/5页
文件大小: 218K
代理商: IN74AC573DW
IN74AC573
459
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, Input t
r
=t
f
=3.0 ns)
V
CC
V
*
Guaranteed Limits
25
°
C
Symbol
Parameter
-40
°
C to
85
°
C
Min
Unit
Min
Max
Max
t
PLH
Propagation Delay, Input D to Output Q
(Figure 1)
3.3
5.0
2.5
2.5
13.0
10.0
2.0
2.0
15.0
11.5
ns
t
PHL
Propagation Delay, Input D to Output Q
(Figure 1)
3.3
5.0
2.5
2.5
12.0
9.5
2.0
2.0
14.0
11.0
ns
t
PLH
Propagation Delay, Latch Enable to Q
(Figure 2)
3.3
5.0
2.5
2.5
13.0
9.5
2.0
2.0
15.0
11.0
ns
t
PHL
Propagation Delay, Latch Enable to Q
(Figure 2)
3.3
5.0
2.5
2.5
12.0
8.5
2.0
2.0
14.0
10.0
ns
t
PZH
Propagation Delay, Output Enable to Q
(Figure 3)
3.3
5.0
2.5
2.5
11.0
9.0
2.0
2.0
12.0
10.0
ns
t
PZL
Propagation Delay, Output Enable to Q
(Figure 3)
3.3
5.0
2.5
2.5
11.0
8.5
2.0
2.0
12.5
9.5
ns
t
PHZ
Propagation Delay, Output Enable to Q
(Figure 3)
3.3
5.0
2.5
2.5
12.5
11.0
2.0
2.0
13.5
12.0
ns
t
PLZ
Propagation Delay, Output Enable to Q
(Figure 3)
3.3
5.0
2.5
2.5
9.5
8.0
2.0
2.0
10.5
9.0
ns
C
IN
Maximum Input Capacitance
5.0
5.0
5.0
pF
Typical @25
°
C,V
CC
=5.0 V
25
C
PD
Power Dissipation Capacitance
pF
*
Voltage Range 3.3 V is 3.3 V
±
0.3 V
Voltage Range 5.0 V is 5.0 V
±
0.5 V
TIMING REQUIREMENTS
(C
L
=50pF, Input t
r
=t
f
=3.0 ns)
V
CC
*
V
Guaranteed Limit
25
°
C
3.5
3.0
Symbol
Parameter
-40
°
C to 85
°
C
4.0
3.5
Unit
t
SU
Minimum Setup Time, Input D to Latch
Enable (Figure 4)
3.3
5.0
ns
t
h
Minimum Hold Time, Latch Enable to
Input D (Figure 4)
3.3
5.0
2.0
2.0
2.0
2.0
ns
t
w
Minimum Pulse Width, Latch Enable
(Figure 2)
3.3
5.0
6.0
4.0
7.0
5.0
ns
*
Voltage Range 3.3 V is 3.3 V
±
0.3 V
Voltage Range 5.0 V is 5.0 V
±
0.5 V
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