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参数资料
| 型号： | IN74ACT652DW |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | OCTAL 3-STATE BUS TRANSCEIVERS AND D FLIP-FLOPS |
| 中文描述： | 八路三态总线收发器和D触发器 |
| 文件页数： | 5/8页 |
| 文件大小： | 282K |
| 代理商： | IN74ACT652DW |
IN74ACT652
5
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC
*
V
Guaranteed Limits
Symbol
Parameter
25
°
C
-40
°
C to
85
°
C
8.0
Unit
t
su
Minimum Setup Time, A or B Data
Port to A-to-B Clock or B-to-A Clock
(Figure 7)
Minimum Hold Time, A-to-B Clock or
B-to-A Clock to A or B Data Port
(Figure 7)
Minimum Pulse Width, A-to-B Clock or
B-to-A Clock (Figure 7)
5.0
7.0
ns
t
h
5.0
2.5
2.5
ns
t
w
5.0
6.0
7.0
ns
TIMING DIAGRAM
相关PDF资料 |
PDF描述 |
|---|---|
| IN74ACT652N | OCTAL 3-STATE BUS TRANSCEIVERS AND D FLIP-FLOPS |
| IN74ACT74D | DUAL D FLIP-FLOP WITH SET AND RESET |
| IN74ACT74N | DUAL D FLIP-FLOP WITH SET AND RESET |
| IN74ACT74 | DUAL D FLIP-FLOP WITH SET AND RESET |
| IN74ACT86 | Quad 2-Input Exclusive OR Gate |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IN74ACT652N | 制造商:INTEGRAL 制造商全称:INTEGRAL 功能描述:OCTAL 3-STATE BUS TRANSCEIVERS AND D FLIP-FLOPS |
| IN74ACT74 | 制造商:INTEGRAL 制造商全称:INTEGRAL 功能描述:DUAL D FLIP-FLOP WITH SET AND RESET |
| IN74ACT74D | 制造商:INTEGRAL 制造商全称:INTEGRAL 功能描述:DUAL D FLIP-FLOP WITH SET AND RESET |
| IN74ACT74N | 制造商:INTEGRAL 制造商全称:INTEGRAL 功能描述:DUAL D FLIP-FLOP WITH SET AND RESET |
| IN74ACT86 | 制造商:INTEGRAL 制造商全称:INTEGRAL 功能描述:Quad 2-Input Exclusive OR Gate |
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