参数资料
型号: IN74HC166N
厂商: INTEGRAL JOINT STOCK COMPANY
英文描述: 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS
中文描述: 8位串行或并行输入/串行输出移位寄存器高性能硅栅CMOS
文件页数: 4/6页
文件大小: 153K
代理商: IN74HC166N
IN74HC166
238
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
25
°
C
to
-55
°
C
6.0
31
36
Symbol
Parameter
85
°
C
125
°
C
Unit
f
max
Minimum Clock Frequency (50% Duty Cycle)
(Figures 2 and 4)
2.0
4.5
6.0
5.0
25
28
4.2
21
25
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock (or Clock
Inhibit) to Q
H
(Figures 2,3 and 4)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
t
PHL
Maximum Propagation Delay , Clear to Q
H
(Figures 1 and 4)
2.0
4.5
6.0
150
30
26
200
40
34
230
48
40
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
16
14
95
20
18
110
25
20
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
Typical @25
°
C,V
CC
=5.0 V
140
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
25
°
C to
-55
°
C
80
16
14
Symbol
Parameter
85
°
C
125
°
C
Unit
t
su
Minimum Setup Time, Shift/Load to
Clock (Figure 3)
2.0
4.5
6.0
100
20
18
120
24
20
ns
t
su
Minimum Setup Time, Data before
Clock (or Clock Inhibit) (Figure 3)
2.0
4.5
6.0
80
16
14
100
20
18
120
24
20
ns
t
w
Minimum Pulse Width, Clock (or
Clock Inhibit) (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
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