参数资料
型号: IN74HC373ADW
厂商: INTEGRAL JOINT STOCK COMPANY
英文描述: Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC -40 to 85
中文描述: 八路三态同相透明锁存器高性能硅栅CMOS
文件页数: 4/5页
文件大小: 117K
代理商: IN74HC373ADW
IN74HC373A
369
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
25
°
C
to
-55
°
C
125
25
21
Symbol
Parameter
85
°
C
125
°
C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
4.5
6.0
155
31
26
190
38
32
ns
t
PLH
, t
PHL
Maximum Propagation Delay , Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay ,Output Enable to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PZL
, t
PZH
Maximum Propagation Delay , Output Enable to
Q (Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
C
IN
C
OUT
Maximum Input Capacitance
-
10
10
10
pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
-
15
15
15
pF
Power Dissipation Capacitance (Per Enabled
Output)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC
2
f+I
CC
V
CC
36
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
85
°
C
Symbol
Parameter
25
°
C to
-55
°
C
25
5.0
5.0
125
°
C
Unit
t
SU
Minimum Setup Time, Input D
to Latch Enable
(Figure 4)
2.0
4.5
6.0
30
6.0
6.0
40
8.0
7.0
ns
t
h
Minimum Hold Time,Latch
Enable to Input D
(Figure 4)
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
t
w
Minimum Pulse Width, Latch
Enable (Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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参数描述
IN74HC373AN 制造商:INTEGRAL 制造商全称:INTEGRAL 功能描述:Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS
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IN74HC393 制造商:INTEGRAL 制造商全称:INTEGRAL 功能描述:DUAL 4-STAGE BINARY RIPPLE COUNTER High-Performance Silicon-Gate CMOS