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参数资料
| 型号： | IN74LS164N |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal Bus Transceivers And Registers With 3-State Outputs 24-SSOP -40 to 85 |
| 中文描述： | 8位Serial-Input/Parallel-Outpout移位寄存器 |
| 文件页数： | 1/4页 |
| 文件大小： | 160K |
| 代理商： | IN74LS164N |
TECHNICAL DATA
1
8-Bit Serial-Input/Parallel-Output
Shift Register
This 8-bit shift register features gated serial inputs and an
asynchronous reset. The gated serial inputs (A and B) permit complete
control over incoming data as a low at either (or both) input(s) inhibits
entry of the new data and resets the first flip flop to the low level at the
next clock pulse. A high level input enables the other input which will
then determine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is high or low, but only information
meeting the setup requirements will be entered clocking occurs or the
low-to-high level transition of the clock input. All inputs are diode-
clamped to minimize transmission-line effects.
Gated (Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Asynchronous Clear
IN74LS164
ORDERING INFORMATION
IN74LS164N Plastic
IN74LS164D SOIC
T
A
=0
°
to 70
°
C
for all packages
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Outputs
Reset
Clock
A1 A2
Q
A
Q
B
... Q
H
L
X
X X
L L ... L
H
X X
no change
H
H D
D Q
An
... Q
Gn
D Q
An
... Q
Gn
L Q
An
... Q
Gn
H
D H
H
L L
D = data input
X = don’t care
Q
An
- Q
Gn
= data shifted from the previous stage on a
rising edge at the clock input.
LOGIC DIAGRAM
PIN 14 =V
CC
PIN 7 = GND
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