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参数资料
| 型号： | IN74LV74N |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Dual D-type flip-flop with set and reset; positive-edge trigger |
| 中文描述： | 带设置和复位功能的双D触发器；上升沿触发 |
| 文件页数： | 1/7页 |
| 文件大小： | 161K |
| 代理商： | IN74LV74N |
TECHNICAL DATA
1
INTEGRAL
Dual D-type flip-flop with set and reset;
positive-edge trigger
The IN74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The IN74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
D
) and (R
D
) inputs;
also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable one set-up time prior to the LOW-to-
HIGH clock transition, for predictable operation. Schmitt-trigger action in
the clock input makes the circuit highly tolerant to slower clock rise and
fall times.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
Supply voltage range: 1.2 to 3.6 V
Low input current: 1.0
μ
à; 0.1
μ
à at ò = 25
°
High Noise Immunity Characteristic of CMOS Devices
IN74LV74
1
14
1
14
N SUFFIX
PLASTIC
D SUFFIX
SOIC
ORDERING INFORMATION
IN74LV74N
IN74LV74D
IZ74LV74
T
A
= -40
°
to 125
°
C for all packages
PIN ASSIGNMENT
Plastic DIP
SOIC
chip
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Outputs
Set
Reset
Clock
Data
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*
H*
H
H
H
H
L
H
H
L
L
H
H
H
L
X
No Change
H
H
H
X
No Change
H
H
X
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
H= high level L = low level
X = don’t care Z = high impedance
1
2
3
5
4
6
7
VCC
RESET 2
14
13
12
11
10
8
9
GND
RESET 1
DATA 1
SET 1
Q1
Q1
DATA2
CLOCK 2
SET 2
Q2
Q2
CLOCK 1
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| IN74LVU04D | CERAMIC CHIP/MIL-PRF-55681 |
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