参数资料
型号: IP1202TRPBF
厂商: International Rectifier
文件页数: 12/29页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 30A 198BGA
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 750
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 5 V
输入电压: 5.5 V ~ 13.2 V
频率 - 开关: 200kHz ~ 400kHz
电流 - 输出: 30A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 198-BGA(161 凸块)
包装: 带卷 (TR)
供应商设备封装: BGA(15.5x9.25)
iP1202PbF
iP1202
iP1202PbF User?s Design Guidelines
The iP1202PbF can be configured as a dual channel
15A or parallel single 30A power block consisting of
optimized power semiconductors, PWM control and
its associated passive components. It is based on a
synchronous buck topology and offers an optimized
solution where space, efficiency and noise caused
by parasitics are of concern. The phase shifted, two
output power block operates with fixed frequency volt-
age mode control and can be configured to operate
as a dual output or paralleled single output with cur-
rent sharing. The iP1202PbF components are inte-
grated in a ball grid array (BGA) package.
V IN
The input operating voltage range of the iP1202PbF
is 5.5V to 13.2V. Both channels of the power block
have a common input.
Enabling the Outputs
This threshold voltage should be taken into consid-
eration when designing sequencing profiles using
the iP1202PbF as it will effect start-up delays and
ramp-times.
For proper implementation of sequencing of outputs
using the iP1202PbF, refer to IR Application Note
AN-1053 - Power sequencing techniques using
iP1201 and iP1202PbF.
Iss
SS1/SS2
iP1202PbF
Css
The ENABLE pin turns on and turns off both outputs
of the iP1202PbF simultaneously. The iP1202PbF
outputs will be turned off by floating the ENABLE pin.
ENABLE low will start the outputs. The converter can
also be shutdown by pulling the soft-start pins to
PGND through a logic level MOSFET the drain of
which connects to the soft start pin (see Fig.12). This
feature can be useful if sequencing or different start-
up timing of the outputs are required. In situations
where the output has undergone a latched shutdown
due to overvoltage or overcurrent, cycling ENABLE
will reset the outputs. Cycling soft start pins will not
unlatch the outputs.
Fig. 12: Soft Start/Enable Circuit
0.8Vtyp
V Css
V OUT
Fig. 13: Power Up Threshold
3V
Dual Soft Start
The Soft Start function provides a controlled rise of
the output voltage, thus limiting the inrush current
during start-up. The iP1202PbF provides two inde-
pendent soft start functions. The soft start pins can
be connected to the soft start capacitors to provide
different start-up and sequencing profiles.
Each soft start function has an internal 25uA +/-20%
current source that charges the external soft start
capacitor C ss up to 3V. During power-up, the output
voltage starts ramping up only after the charging
voltage across the C ss capacitor has reached a
0.8Vtyp threshold, as shown in Fig. 13.
12
Mode of Operation
The iP1202PbF can be configured to provide either
two independent dual outputs or single paralleled out-
put with current share. In dual output mode, the two
error amplifiers of the PWM controller operate inde-
pendently. Each output voltage of the iP1202PbF
block is controlled by its own error amplifier. The out-
put of the error amplifier and the internally generated
ramp signal are compared to produce PWM pulses
of fixed frequency that drive the internal power
switches. In this mode, the VP-ref pin must be con-
nected to Vref pin. Vref pin is the internally generated
0.8V reference input of first error amplifier . Refer to
the internal block diagram of the iP1202PbF in Fig.1.
In single output mode, one error amplifier controls
the output voltage and the other amplifier monitors
www.irf.com
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