参数资料
型号: IP1203
厂商: International Rectifier
文件页数: 1/23页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 15A 24LGA
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 10
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 8 V
输入电压: 5.5 V ~ 13.2 V
频率 - 开关: 200kHz ~ 400kHz
电流 - 输出: 15A
同步整流器:
工作温度: -10°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-LGA
包装: 托盘
供应商设备封装: LGA(9x9)
配用: IRDCIP1203-A-ND - IP1203 REFERENCE DESIGN KIT
其它名称: *IP1203
PD- 96921C
iP1203
Single Output Full Function
Synchronous Buck Power Block
Integrated Power Semiconductors,
Features
PWM Control & Passives
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5.5V to 13.2V Input Voltage
0.8V to 8V Output Voltage
15A Maximum Load Capability
200-400kHz Nominal Switching Frequency
Over Current Hiccup
External Synchronization Capable
Overvoltage Protection
Over Temperature Protection
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Internal Features Minimize Layout Sensitivity
Very Small Outline 9mm x 9mm x 2.3mm
iP1203 Power Block
Description
The iP1203 is a fully optimized solution for medium current synchronous buck applications requiring up to 15A.
It includes full function PWM control, with optimized power semiconductor chipsets and associated passives,
achieving high power density. Very few external components are required to create a complete synchronous
buck power supply.
iPOWIR ? technology offers designers an innovative space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers benefits
in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat
transfer and component selection.
iP1203 Simplified Application Schematic
Pin Number
(See Page 18)
1, 23
Pin Name
V IN
Pin Description
Input voltage connection pins
V
V
V
SW
IN
IN
CC_bypass
OC
V
FB
V OUT
2,3,4,5,7,17,20,21
6
8
9
10
PGND
V CC_bypass
SS
CC
FB
Power Ground pins
PWM controller power supply pin. Internally generated.
Requires a 2.2μf external bypass capacitor
Soft start pin. External capacitor provides soft start. Pulling soft start pin low
will disable the output. Cannot be cycled to unlatch OVP trip
Output of the error amplifier
Inverting input of the error amplifier
FB
PGOOD
SS
iP1203
S
11
12
FB s
R T
Output overvoltage sense pin.
Switching frequency setting pin. For R T selection, refer to Fig.9 of the
datasheet
R T
CC
13
14
15
PGOOD
V REF
SYNC
Power Good pin. Open collector, requires external pulll-up. If function not
needed, pin can be left floating
Non inverting input of the error amplifier (reference Voltage pin). Connect a
100pF cap from this pin to PGND.
External Clock synchronization pin. Set free running frequency to 80% of
the SYNC frequency. When not in use, leave pin floating
REF
SYNC
V
16
18,19
22
24
OCSET
V SW
V SWs
V INs
Output overcurrent trip threshold pin
Output inductor connection pins
Test pad, for internal use, short to VSW
Test pad, for internal use, short to V IN
04/08/05
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