参数资料
型号: IP2001
厂商: International Rectifier
文件页数: 1/10页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 20A 144BGA
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 10
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.9 V ~ 3.3 V
输入电压: 3.3 V ~ 12 V
频率 - 开关: 150kHz ~ 1.0MHz
电流 - 输出: 20A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 144-BGA(134 凸块)
包装: 管件
供应商设备封装: BGA(11x11)
其它名称: *IP2001
PD - 94089F
iP2001
Synchronous Buck
Multiphase Optimized BGA Power Block
Integrated Power Semiconductors, Drivers & Passives
Features:
?
20A continuous output current with no derating
?
?
?
?
up to T PCB = 90°C
Very small 11mm x 11mm x 3mm profile
Internal features minimize layout sensitivity *
Optimized for very low power losses
3.3 to 12V input voltage
iP2001 Power Block
Description
The iP2001 is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 3mm
BGA power block. The only additional components required for a complete multiphase converter are a PWM
IC, the external inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component
integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized
internally for layout, heat transfer and component selection.
iP2001 Internal Block Diagram
V IN
PRDY
ENABLE
MOSFET
PWM
Driver with
dead time
V SW
V DD
SGND
control
PGND
* All of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR Block. There are no concerns about double pulsing,
unwanted shutdown, or other malfunctions which often occur in switching power supplies. The iPOWIR Block will function normally without any additional input power
supply bypass capacitors. However, for reliable long term operation it is recommended that the adequate amount of input decoupling is provided on the V IN pin. No
additional bypassing is required on the V DD pin.
www.irf.com
03/10/03
1
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