参数资料
型号: IP2002TR
厂商: International Rectifier
文件页数: 3/12页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 30A 144BGA
标准包装: 1,000
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.9 V ~ 3.3 V
输入电压: 3 V ~ 13.2 V
频率 - 开关: 150kHz ~ 1.0MHz
电流 - 输出: 30A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 144-BGA(134 凸块)
包装: 带卷 (TR)
供应商设备封装: BGA(11x11)
iP2002
Pin Description Table
Pin Name
V DD
V IN
PGND
V SW
SGND
ENABLE
PRDY
PWM
Ball Designator
A1 – A3, B1 – B3
A5 – A12, B5 – B12,
C5 - C10
C11, C12, D11, D12, E11,
E12, F6, F7, F12, G6, G7,
G12, H6, H7, H12, J6, J7, J12,
K5 – K7, K12, L5, L6, L12,
M5 – M7, M12
D5 – D10, E5 – E10,
F8 – F11, G8 – G11,
H8 – H11, J8 – J11,
K8 – K11, L8 – L11,
M8 – M11
C1 – C3, D1 –D3, E1 –E3
F1
K1
H1
Pin Function
Supply voltage for the internal circuitry.
Input voltage for the DC-DC converter.
Power Ground - connection to the ground of
bulk and filter capacitors.
Switching Node - connection to the output
inductor.
Signal Ground.
When set to logic level high, internal
circuitry of the device is enabled. When set
to logic level low, the PRDY pin is forced
low, the Control and Sychronous switches are
turned off, and the supply current is less than
10μA.
Power Ready - This pin indicates the status of
ENABLE or V DD . This output will be driven
low when ENABLE is logic low or when V DD
is less than 4.4V (typ.). When ENABLE is
logic high and V DD is greater than 4.4V
(typ.), this output is driven high. This output
has a 10mA source and 1mA sink capability.
TTL-level input signal to MOSFET drivers.
G4, H2 – H4, J1, J2 – J4, K3, should be attached only to dead copper.
NC
www.irf.com
B4, C4, D4, E4, F2 – F4, G2 –
L1, L2, M1 – M4
This pin is not for electrical connection. It
3
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