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参数资料
| 型号： | IP82C52 |
| 厂商： | Intersil |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC UART/BRG PERIPHERAL 28-DIP |
| 标准包装： | 78 |
| 特点： | 单芯片 UART/BRG |
| 通道数： | 1，UART |
| 规程： | RS232C |
| 电源电压： | 4.5 V ~ 5.5 V |
| 带并行端口： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 28-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 28-PDIP |
| 包装： | 管件 |
17
FN2950.3
April 26, 2006
NOTES:
1. TBRE bit D6 in USR is updated each time TBRE changes state.
2. A. With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR goes high.
B. With TR initially full, TCLTH(TBRE) occurs from the trailing edge of the 15th CO(BRG) in the last Stop bit provided WR went high by the
trailing edge of the 12th CO(BRG) in the last Stop bit.
3. A. With TR (Transmitter Register) initially empty, TDTX occurs from the 5th falling edge of CO(BRG) after WR goes high.
B. With TR initially full, TDTX occurs from the trailing edge of the 16th CO(BRG) in the last Stop bit provided WR went high by the trailing edge
of the 12th CO(BRG) in the last Stop bit.
4. TCTHX is time before end of last Stop bit by which CTS must be inactive (high) to prevent transmission of the character waiting in TBR.
5. With CTS high (disable transmit) and TBR full, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after CTS goes low.
6. With CTS high (disable transmit) and TBR full, TDTX occurs from the 5th falling edge of CO(BRG) after CTS goes low.
FIGURE 19. RECEIVE TIMING
UART Timing Characterization (Continued)
CO(BRG)
SDI
DR
INTR
11
12
13
14
15
16
1/I
2/I
3/I
(23)
TRLIL
(26)
TRLDL
USR
RBR
START BIT / IDLE
(25)
TDRH
(21)
TIHF
RD
LAST STOP BIT
NOTE 1
NOTE 2
82C52
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| IP82C52/+ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:UART |
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