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参数资料
| 型号： | IP82C59A-12 |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 中断控制器 |
| 英文描述： | CMOS Priority Interrupt Controller |
| 中文描述： | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, PDIP28 |
| 文件页数： | 3/20页 |
| 文件大小： | 152K |
| 代理商： | IP82C59A-12 |
4-3
Functional Description
Interrupts in Microcomputer Systems
Microcomputer system design requires that I/O devices such
as keyboards, displays, sensors and other components
receive servicing in an efficient manner so that large
amounts of the total system tasks can be assumed by the
microcomputer with little or no effect on throughput.
The most common method of servicing such devices is the
Polled approach. This is where the processor must test each
device in sequence and in effect “ask” each one if it needs
servicing. It is easy to see that a large portion of the main
program is looping through this continuous polling cycle and
that such a method would have a serious, detrimental effect
on system throughput, thus, limiting the tasks that could be
assumed by the microcomputer and reducing the cost effec-
tiveness of using such devices.
Pin Description
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
V
CC
28
I
V
CC
: The +5V power supply pin. A 0.1
μ
F capacitor between pins 28 and 14 is recommended for
decoupling.
GND
14
I
GROUND
CS
1
I
CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the
82C59A. INTA functions are independent of CS.
WR
2
I
WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from
the CPU.
RD
3
I
READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus
for the CPU.
D7 - D0
4 - 11
I/O
BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via
this bus.
CAS0 - CAS2
12, 13, 15
I/O
CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A struc-
ture. These pins are outputs for a master 82C59A and inputs for a slave 82C59A.
SP/EN
16
I/O
SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it
can be used as an output to control buffer transceivers (EN). When not in the Buffered Mode it is
used as an input to designate a master (SP = 1) or slave (SP = 0).
INT
17
O
INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to inter-
rupt the CPU, thus, it is connected to the CPU's interrupt pin.
IR0 - IR7
18 - 25
I
INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an
IR input (low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just
by a high level on an IR input (Level Triggered Mode). Internal pull-up resistors are implemented
on IR0 - 7.
INTA
26
I
INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the
data bus by a sequence of interrupt acknowledge pulses issued by the CPU.
A0
27
I
ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the
82C59A to decipher various Command Words the CPU writes and status the CPU wishes to read.
It is typically connected to the CPU A0 address line (A1 for 80C86/88/286).
ROM
I/O (N)
I/O (2)
I/O (1)
RAM
CPU
CPU - DRIVEN
MULTIPLEXER
FIGURE 2. POLLED METHOD
82C59A
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相关代理商/技术参数 |
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| IP82C59A-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
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