参数资料
型号: IR21571
厂商: International Rectifier
文件页数: 12/18页
文件大小: 0K
描述: IC BALLAST CONTROL 16-DIP
其它有关文件: 16 Lead PDIP
标准包装: 25
类型: 镇流器控制器
频率: 45.5 ~ 50.5 kHz
电流 - 电源: 5.5mA
电流 - 输出: 500mA
电源电压: 11.4 V ~ 15.6 V
工作温度: -40°C ~ 125°C
封装/外壳: 16-DIP(0.300",7.62mm)
供应商设备封装: 16-DIP
包装: 管件
其它名称: *IR21571
IR21571(S) & (PbF)
Lamp Protection & Automatic Restart Circuitry Operation
Three leads on the IR21571 are used for protection, as shown in Figure 10 below. These are V DC (dc bus
monitor), S D (unlatched shutdown), C S (latched shutdown) and OC (CS+ threshold programming).
+V BUS
R2
VDC
1
3.0V
S
Q
R1
C1
5.1V
R
Q
from oscillator
section
CPH
1.0uA
T
Q
2
R
Q
Q2
7.6V
5.1V
R3
4.0V
DT
7
Q
Q
S
R
Q
Q
D
CLK
R
0.2V
10
CS
R CS
V CC
7.6V
OC
8
50uA
UNDER-
VOLTAGE
DETECT
OVER-
TEMP
DETECT
9
SD
R4
R5
R OC
7.6V
2.0V
7.6V
C2
from lower
lamp cathode
Figure 10: Lamp protection & automatic restart circuitry block diagram with external component connection.
Sensing the DC Bus Voltage
The first of these protection leads senses the voltage
on the DC bus by means of an external resistor
divider and an internal comparator with hysteresis.
When power is first supplied to the IC at system
startup, 3 conditions are required before oscillation
is initiated: 1.) the voltage on the V CC lead must exceed
the rising undervoltage lockout threshold (11.5V),
2.) the voltage at the V DC lead must exceed 5.1V, and
3.) the voltage on the SD lead must be below
approximately 1.85V. If a low dc bus condition occurs
during normal operation, or if power to the ballast is
shut off, the dc bus will collapse prior to the V CC of the
chip (assuming the V CC is derived from a charge
12
pump off of the output of the half-bridge). In this
case, the voltage on the V DC lead will shut the oscillator
off, thereby protecting the power transistors from
potentially hazardous hard switching. Approximately
2V of hysteresis has been designed into the internal
comparator sensing the V DC lead, in order to account
for variations in the dc bus voltage under varying
load conditions. When the dc bus recovers, the chip
restarts from the beginning of the control sequence,
as shown in timing diagram Figure 11.
www.irf.com
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