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参数资料
| 型号： | IR2177SPBF |
| 厂商： | International Rectifier |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC CURRENT SENSE 0.2% 16SOIC |
| 标准包装： | 45 |
| 功能： | 电流感应 |
| 精确度： | ±0.2% |
| 输入电压： | 8 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
IR2277S/IR2177S (PbF)
Filter AC characteristic
IR2177/2277 signal path can be considered as
composed by three stages in series (see Figure 17).
The first two stages perform the filtering action.
Stage 1 (input filter) implements the filtering action
originating the transfer function shown in Figure 18.
The input filter is a self-adaptive reset integrator
which performs an accurate ripple cancellation. This
stage extracts automatically the PWM frequency
from Sync signal and puts transmission zeros at
even harmonics, rejecting the unwanted PWM
noise.
The following timing diagram shows the principle by
which even harmonics are rejected (Figure 16).
As can be seen from Figure 18, the odd harmonics
are rejected as a first order low pass filter with a
single pole placed in f PWM .
The input filter group delay in the pass-band is very
low (see GD on AC electrical characteristics) due to
the beneficial action of the zeroes.
The second stage samples the result of the first
stage at double Sync frequency. This action can be
used to fully remove the odd harmonics from the
input signal.
To perform this cancellation it is necessary a shift of
90 degrees of the SYNC signal with respect to the
triangular carrier edges (SYNC2).
The following timing diagrams show the principle of
odd harmonics cancellation (Figure 19), in which
SYNC2 allows the sampling of stage 1 output
during odd harmonic zero crossings.
Odd harmonic cancellation using SYNC2 (i.e. 90
degree shifted SYNC signal) signal will introduce
Tsync/4 additional propagation delay.
Anther way to obtain the same result (odd
harmonics cancellation) can be achieved by
controller computing the average of two consecutive
PO results using SYNC1 (SYNC is in this case
aligned to triangular edges, i.e. 0 degree shift).
This method is suitable for most symmetric (center
aligned) PWM schemes.
For this particular PWM scheme another suitable
solution is driving the IR2x77 with a half frequency
SYNC signal (f sync =f PWM /2).
In this case the cut frequency of the input filter is
reduced by half allowing zeroes to be put at f PWM
multiples (i.e. even and odd harmonics cancellation,
no more computational effort needed by the
controller).
Figure 16: Even harmonic cancellation principle
Figure 17: Simplified block diagram
15
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