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参数资料
| 型号： | IR3086M |
| 厂商： | International Rectifier |
| 文件页数： | 7/34页 |
| 文件大小： | 0K |
| 描述： | IC PHASE CONTROLLER 20-MLPQ |
| 标准包装： | 5 |
| 系列： | XPhase™ |
| 应用： | 处理器 |
| 电流 - 电源： | 10mA |
| 电源电压： | 8.4 V ~ 14 V |
| 工作温度： | 0°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-MLPQ |
| 供应商设备封装： | 20-MLPQ（4x4） |
| 包装： | 剪切带 (CT) |
| 其它名称： | *IR3086M |
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IR3086
PWM Control Method
The PWM block diagram of the XPhase TM architecture is shown in Figure 2. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used
for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the
slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change
with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change
due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes
in load current.
VIN
CONTROL IC
SYSTEM
PHASE IC
50%
DUTY
CYCLE
RAMP GENERATOR
VPEAK
VVALLEY
RMPOUT
RPHS1
BIASIN
RAMPIN+
RAMPIN-
REFERENCE
VOLTAGE
CLOCK
PULSE
GENERATOR
PWM
COMPARATOR
PWM
LATCH
S
RESET
DOMINANT
GATEH
VOSNS+
VOUT
+
-
VBIAS
REGULATOR
VDAC
VBIAS
VDAC
VOSNS-
EAOUT
RPHS2
RPWMRMP
CPWMRMP
EAIN
PWMRMP
SCOMP
CSCOMP
SHARE
ADJUST
-
+
ENABLE
RAMP
DISCHARGE
CLAMP
R
BODY
BRAKING
COMPARATOR
GATEL
COUT
GND
VOSNS-
ERROR
ERROR
AMPLIFIER
X
0.91
IFB
AMP
IROSC
FB
RVFB
RDRP
ISHARE
10K
+
-
20mV
CURRENT
SENSE
AMPLIFIER
X34
CSIN+
CSIN-
CCS
RCS
VDRP
AMP
VDRP
IIN
DACIN
SYSTEM
PHASE IC
BIASIN
REFERENCE
VOLTAGE
PWM
RPHS1
RAMPIN+
RAMPIN-
EAIN
CLOCK
PULSE
GENERATOR
PWM
COMPARATOR
-
+
LATCH
S
RESET
DOMINANT
R
GATEH
GATEL
RPHS2
ENABLE
RPWMRMP
PWMRMP
BODY
CPWMRMP
SCOMP
CSCOMP
SHARE
ADJUST
RAMP
DISCHARGE
CLAMP
BRAKING
COMPARATOR
ERROR
AMPLIFIER
X
0.91
ISHARE
10K
+
20mV
CURRENT
SENSE
AMPLIFIER
CSIN+
-
X34
CSIN-
CCS
RCS
DACIN
Figure 2. PWM Block Diagram
Frequency and Phase Timing Control
An oscillator with programmable frequency is located in the Control IC. The output of the oscillator is a 50% duty
cycle triangle waveform with peak and valley voltages of approximately 5V and 1V respectively. This signal is used
to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by
resistor divider R PHS1 and R PHS2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A
comparator in the Phase ICs detects the crossing of the oscillator waveform over the voltage generated by the
resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS
voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note
that both slopes of the triangle waveform can be used for phase timing by swapping the RMPIN+ and RMPIN– pins,
as shown in Figure 2.
Page 7 of 34
9/30 /04
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