参数资料
型号: IR3092MTRPBF
厂商: International Rectifier
文件页数: 10/37页
文件大小: 0K
描述: IC CONTROLLER 2PHASE 48-MLPQ
标准包装: 3,000
应用: VID 电压编程器
电源电压: 7.3 V ~ 21 V
电流 - 电源: 29mA
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 48-MLPQ
供应商设备封装: 48-MLPQ(7x7)
包装: 带卷 (TR)
IR3092PbF
IR3092 THEORY OF OPERATION
IOVP
VCC
ON
OVP
ROSC
FB
IROSC
EAOUT
VCCH1
LGND
SETBIAS
BIASOUT
5VUVL
4 X IROSC
-
UVL
UVL
-
+
7.8V START
7.3V STOP
45k
IROSC
1.243
OVP Comparator
FB
IROSC
CLK1
CLK2
Oscillator
BB DISABLE COMPARATOR
RESET DOMINANT
S
Q
QB
R
RSFF
IROSC/2
IN
OL_IN
GateHI
OL_IN
GATEHI
OL_OUT
OL_OUT
GATEHI1
VCCL
+
4.300V START
AMD=450mV
INTEL=150mV
80mV
PWM COMPARATOR
10p
0.7V
IN
GateLO
GATELO
GATEL1
PWRGD
4.125V STOP
VDAC
0% DUTY CYCLE
VDAC
PGND1
OCSET
OVER CURRENT
0.55V
summer
X25
CSINP1
IROSC
-
DELAY
1.3V
+
Sof tStart_Clamp
DISABLE
VDAC
X25
-
CSINM
+
-
+
CSINP2
240mV chrg, 210mV dischrg
Error_Amp
Share Adjust Error Amp
summer
4V
55U
OFF
EQUAL DUTY CY CLE COMPARATOR
+
-
VDRP
SS
-
RESET DOMINANT
SCOMP
3V
ENABLE
5.5U
15k
-
45U
-
+
0.26V
ON
Discharge Comparator
1.9us
BLANKING
FAULT LATCH
S
R
SET DOMINANT
DAC DEFAULTS TO VR10
WITH VID_SEL GROUNDED
0.7V
+
DAC BUFFER
-
+
IROSC
RSFF
S
R
Q
QB
IROSC
IN
OL_IN
GATEHI
OL_OUT
VCCH2
GATEH2
AMD=1.5V
INTEL=0.6V
+
F11111
ATHLON_DAC
OPTERON_DAC
DAC
OUT
FAST DAC
PWM COMPARATOR
GateHI
VOSNS-
18uA
VCCL
VID_SEL
3.4V
4.9V
5V
3.3V
1
H FORCES IROSC/2 AT SS<0.7V
0 TO IROSC*3/4
10p
0.7V
U18
OL_IN
IN
GateLO
OL_OUT
GATELO
GATEL2
1.2V
60K
110K
PGND2
VID0
VID1
VID2
VID3
VID4
VID5
VOSNS-
VDAC
Figure 1 – IR3092 Block Diagram
PWM Operation
The IR3092 is a fully integrated 2 phase interleaved PWM control IC which uses voltage mode control with trailing edge
modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the control IC is used for the voltage control loop.
The PWM block diagram of the IR3092 is shown in Figure 2.
Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to increase, the
low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 10pf capacitor is charged
by a current source that ’s proportional to the switching frequency resulting in a ramp rate of 57mV per percent duty cycle.
For example, if the steady-state operating switch node duty cycle is 10%, then the internal ramp amplitude is typically
570mV from the starting point (or floor) to the crossing of the EAOUT control voltage. When the PWM ramp voltage
exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns off the high side driver, turns on the low side
driver, and discharges the PWM ramp to 0.7V until the next clock pulse.
Page 10 of 37
09/07/05
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