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参数资料
| 型号： | IR3651SPBF |
| 厂商： | International Rectifier |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 14-SOIC |
| 标准包装： | 55 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 460kHz |
| 占空比： | 80% |
| 电源电压： | 4.5 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 配用： | IRDC3651-ND - KIT REF DESIGN SYNCH BUCK REG |
IR3651SPBF
Based on the frequency of the zero generated by
output capacitor and its ESR versus crossover
frequency, the compensation type can be
different. The table below shows the
compensation types and location of crossover
frequency.
The following design rules will give a crossover
frequency approximately one-tenth of the
switching frequency. The higher the band width,
the potentially faster the load transient response.
The DC gain will be large enough to provide high
DC-regulation accuracy (typically -5dB to -12dB).
The phase margin should be greater than 45 o for
Compensator
type
TypII(PI)
F ESR vs. F o
F LC <F ESR <F o <F s/2
Output
capacitor
Electrolytic
, Tantalum
overall stability.
Desired Phase Margin:
Θ max =
π
3
F LC <F o <F ESR <F s/2
Method A
F LC <F o <F s/2 <F ESR
C 4 =
;
TypeIII(PID) Tantalum,
ceramic
TypeIII(PID) Ceramic
Method B
Table1- The compensation type and location
Calculate C 4 , C 3 and C 7 :
1
2 π * F Z1 * R 3
of F ESR versus F o
The details of these compensation types are
discussed in application note AN-1043 which can
C 3 =
1
2 π * F P 3 * R 3
;
be downloaded from IR Web-Site.
For F LC <F o <F s/2 <F ESR
C 7 =
2 π * F o * L o * C o * V osc
R 3 * V in
;
typeIII method B is selected to place the pole and
zeros.
Calculate R 10 , R 8 and R 9 :
F o < F ESR and F o ≤ ( 1/5 ~ 1/10 ) * F s
R 10 =
1
2 π * C 7 * F P 2
;
F Z 2 = F o *
1 ? Sin Θ
1 + Sin Θ
R 8 =
1
2 π * C 7 * F Z 2
? R 10 ;
F P 2 = F o *
1 + Sin Θ
1 ? Sin Θ
R 9 =
V ref
V o ? V ref
* R 8 ;
Select : F Z1 = 0 . 5 * F Z 2 and F P3 = 0.5 * F s
Programming the Current-Limit
The Current-Limit threshold can be set by
R 3 ≥
2
g m
;
connecting a resistor (R SET ) from drain of low
side MOSFET to the OCSet pin. The resistor
can be calculated by using equation (3).
The R DS(on)
has a positive temperature
coefficient and it should be considered for the
worse case operation. This resistor must be
placed close to the IC, place a small ceramic
capacitor from this pin to ground for noise
rejection purposes.
06/08/2011
I SET = I L ( critical ) =
R OCSet ? I OCSet
R DS ( on )
--( 3 )
17
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