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| 型号： | IR3821MTRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 15/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 7A 15QFN |
| 产品培训模块： | SupIRBuck™ Integrated Point-of-Load Regulators SupIRBuck? Family and POL Design Tools Overview |
| 标准包装： | 1 |
| 系列： | SupIRBuck™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 12 V |
| 输入电压： | 2.5 V ~ 21 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 600kHz |
| 电流 - 输出： | 7A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 15-PowerVQFN |
| 包装： | 标准包装 |
| 供应商设备封装： | PQFN（5x6） |
| 产品目录页面： | 1384 (CN2011-ZH PDF) |
| 其它名称： | IR3821MTRPBFDKR |
PD-60331
IR3821MPbF
Based on the frequency of the zero generated by
the output capacitor and its ESR versus
crossover frequency, the compensation type can
be different. The table below shows the
compensation types and location of crossover
frequency.
Select crossover frequency:
F o < F ESR and F o ≤ ( 1/5 ~ 1/10 ) * F s
Fo=80kHz
Since: FLC<Fo<Fs/2<FESR , typeIII method B is
selected to place the poles and zeros.
Compensator
type
Typ II(PI)
Type III(PID)
Method A
Type III(PID)
Method B
F ESR vs. F o
F LC <F ESR <F o <F s/2
F LC <F o <F ESR <F s/2
F LC <F o <F s/2 <F ESR
Output
capacitor
Electrolytic
, Tantalum
Tantalum,
ceramic
Ceramic
The following design rules will give a crossover
frequency approximately one-tenth of the
switching frequency. The higher the band width,
the potentially faster the load transient response.
The DC gain will be large enough to provide high
DC-regulation accuracy (typically -5dB to -12dB).
The phase margin should be greater than 45 o for
overall stability.
Table1- The compensation type and location
of F ESR versus F o
Desired Phase Boost: Θ max = 70 o
The details of these compensation types are
discussed in application note AN-1043 which can
F Z 2 = F o *
1 - Sin Θ
1 + Sin Θ
F P 2 = F o *
be downloaded from IR’s website at www.irf.com.
For this design we have:
V in =12V
V o =1.8V
V osc =1.25V
V ref =0.6V
g m =1000umoh
L o =1.0uH
C o =6x22uF, ESR=0.8mOhm
F Z 2 = 14 . 1 kHz
1 + Sin Θ
1 - Sin Θ
F P 2 = 453 . 7 kHz
Select : F Z1 = 0 . 5 * F Z 2 and F P3 = 0.5 * F s
Select : C 7 = 180pF
2 π * F o * L o * C o * V OSC
F s =600kHz
The value of the capacitance used in the
compensator design must be the small signal
R 3 =
C 7 * V in
Select : R 3 = 21K Ω
, R 3 = 20 . 94 K ? , check R 3 ≥
2
g m
value. For instance, the small signal capacitance
of the 22uF capacitor used in this design is 12uF
Calculate C 4 and C 3 :
at 1.8 VDC bias and 600 kHz frequency. It is this
value that must be used for all computations
related to the compensation. The small signal
value may be obtained from the manufacturer’s
datasheets, design tools or SPICE models.
C 4 =
C 3 =
1
2 π * F Z1 * R 3
1
2 π * F P 3 * R 3
; C 4 = 1.07nF, Select : C 4 = 1 . 0 nF
; C 3 = 25 . 26 pF , Select : C 3 = 22 pF
; R 10 = 1 . 95 K Ω , check R 10 ≥
R 10 =
Alternatively, they may also be inferred from
measuring the power stage transfer function of
the converter and measuring the double pole
frequency FLC and using equation (11) to
compute the small signal Co.
Calculate R 10 , R 8 and R 9 :
1
2 π * C 7 * F P 2
Select : R 10 = 1 . 96 K Ω
1
g m
These result to:
R 8 =
1
2 π * C 7 * F Z 2
- R 10 ; R 8 = 60 . 72 K Ω , Select : R 8 = 60 . 4 K Ω
F LC =18.76kHz
F ESR =4.4MHz
R 9 =
V ref
V o - V ref
* R 8 ; R 9 = 30 . 20 K Ω , Select : R 9 = 30 . 1 K Ω
F s/2 =300kHz
11/04/08
15
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