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参数资料
| 型号： | IR3822MTRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 16/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 15QFN |
| 产品培训模块： | SupIRBuck™ Integrated Point-of-Load Regulators SupIRBuck? Family and POL Design Tools Overview |
| 标准包装： | 1 |
| 系列： | SupIRBuck™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 12 V |
| 输入电压： | 2.5 V ~ 21 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 600kHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 15-PowerVQFN |
| 包装： | 标准包装 |
| 供应商设备封装： | PQFN（5x6） |
| 产品目录页面： | 1384 (CN2011-ZH PDF) |
| 其它名称： | IR3822MTRPBFDKR |
PD-60333
IR3822MPBF
The R DS(on)
Programming the Current-Limit
The Current-Limit threshold can be set by
connecting a resistor (R SET ) from drain of the
low-side MOSFET to the OCSet pin. The
resistor can be calculated by using equation (3).
has a positive temperature
coefficient and it should be considered for the
worse case operation. This resistor must be
placed close to the IC, place a small ceramic
capacitor from this pin to power ground (PGnd)
for noise rejection purposes.
Layout Consideration
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with less than expected results.
Start to place the power components, making all
the connection in the top layer with wide, copper
filled areas.
The inductor, output capacitor and the IR3822
should be as close to each other as possible.
This helps to reduce the EMI radiated by the
I SET = I L(critical ) =
R OCSet ? I OCSet
R DS(on)
- -(3)
power traces due to the high switching currents
through them. Place the input capacitor directly to
the Vin pin of IR3822. To reduce the ESR replace
the single input capacitor with two parallel units.
The feedback part of the system should be kept
I SET = (I o ? 1 . 5 ) +
Δ i = ( V in - V o ) ?
R DS(on) = 18m ? ? υ = 18m ? ? 1 .5 = 27m ?
where :
υ : Temperatur e Dependency
Note : Use 24 m ? for low - side MOSFET
if 5V is used for V cc
Δ i
2
where :
I o : Max Output Current
Δ i : Inductor ripple current
V o
V in ? L ? F s
I SET = (4A ? 1.5) + 0 . 85 A = 6.85A
R OCSet = R 7 = 9.31K ?
Setting the Power Good Threshold
Power Good threshold can be programmed by
using two external resistors (see figure 16).
The following formula can be used to set the
threshold:
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vcc and Vc should be close to their
respective pins. It is important to place the
feedback components including feedback
resistors and compensation components close to
Fb and Comp pins.
In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are
referenced. The goal is to localize the high
current path to a separate loop that does not
interfere with the more sensitive analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
The Power QFN is a thermally enhanced
package. Based on thermal performance it is
recommended to use at least a 4-layers PCB. To
effectively remove heat from the device the
exposed pad should be connected to the ground
plane using vias.
R 2 =
0 . 38 V
0 . 9 *V out - 0 . 38 V
*R 1
--( 19 )
Where:
0.38V is reference of the internal comparator
0.9*Vout is selectable threshold for power good,
for this design it is 1.62V.
Select R 1 =10KOhm
Using (18): R 2 =3.06KOhm
Select R 2 =3.09K
Use a pull up resistor (4.99K) from PGood pin to
Vcc.
11/04/08
16
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