参数资料
型号: IR3842WMTR1PBF
厂商: International Rectifier
文件页数: 18/34页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A 15QFN
产品培训模块: SupIRBuck? Family and POL Design Tools Overview
特色产品: Gen2.1 SupIRBuck? Integrated Voltage Regulators
标准包装: 1
系列: SupIRBuck™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.7 V ~ 14.4 V
输入电压: 1.5 V ~ 16 V
PWM 型: 电压模式
频率 - 开关: 225kHz ~ 1.65MHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 15-PowerVQFN
包装: 标准包装
供应商设备封装: PQFN(5x6)
其它名称: IR3842WMTR1PBFDKR
PD-97659
IR3842WMPbF
Application Information
Design Example:
when an external resistor divider is connected to
the output as shown in figure 11.
Equation (5) can be rewritten as:
R 9 = R 8 ? ? ?
? .......... .......... .......... .... (8)
?
The following example is a typical application for
IR3842W. The application circuit is shown on
page 23.
? V ref
? V o ? V ref
?
?
V in = 12 V ( 13.2V max)
V o = 1.8 V
I o = 4 A
For the calculated values of R8
feedback compensation section.
V OU T
and R9 see
Δ V o ≤ 54mV
F s = 600 kHz
Enabling the IR3842W
As explained earlier, the precise threshold of
IR3624
IR3842W
Fb
R 8
R 9
the Enable lends itself well to implementation of
a UVLO for the Bus Voltage.
V in
Fig. 11. Typical application of the IR3842W for
programming the output voltage
Soft-Start Programming
The soft-start timing can be programmed by
IR3842W
Enable
R 1
R 2
selecting the soft-start capacitance value. From
(1), for a desired start-up time of the converter,
the soft start capacitor can be calculated by
using:
C SS ( μ F ) = T start ( ms ) × 0.02857 .......... (9)
= V EN = 1.2 .......... (5)
V in (min) *
R 2 = R 1
V EN
V o = V ref ? ? ? 1 + 8 ? ? .......... .......... .......... .....(7)
For a typical Enable threshold of V EN = 1.2 V
R 2
R 1 + R 2
.......... (6)
V in( min ) ? V EN
For a V in (min) =10.2V, R 1 =49.9K and R 2 =7.5K is a
good choice.
Programming the frequency
For F s = 600 kHz, select R t = 23.7 k ? , using
Table. 1.
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.7V. The divider is
ratioed to provide 0.7V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
? R ?
? R 9 ?
Rev 13.0
Where T start is the desired start-up time (ms).
For a start-up time of 3.5ms, the soft-start
capacitor will be 0.099 μ F. Choose a 0.1 μ F
ceramic capacitor.
Bootstrap Capacitor Selection
To drive the Control FET, it is necessary to
supply a gate voltage at least 4V greater than
the voltage at the SW pin, which is connected
the source of the Control FET . This is achieved
by using a bootstrap configuration, which
comprises the internal bootstrap diode and an
external bootstrap capacitor (C6), as shown in
Fig .12. The operation of the circuit is as follows:
When the lower MOSFET is turned on, the
capacitor node connected to SW is pulled down
to ground. The capacitor charges towards V cc
through the internal bootstrap diode, which has a
forward voltage drop V D . The voltage V c across
the bootstrap capacitor C6 is approximately
given as
V c ? V cc ? V D .......... .......... ...... (10)
When the upper MOSFET turns on in the next
cycle, the capacitor node connected to SW rises
to the bus voltage V in . However, if the value of
C6 is appropriately chosen,
18
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