参数资料
型号: IRAC1150-D2
厂商: International Rectifier
文件页数: 12/12页
文件大小: 0K
描述: BOARD CONTROL FOR IR1150S
标准包装: 1
系列: µPFC™
主要目的: 电源管理,功率因数校正
已用 IC / 零件: IR1150S
已供物品: 板,文档
相关产品: IR1150SDKR-ND - IC PFC CONTROLLER CCM 8-SOIC
IR1150SPBFDKR-ND - IC PFC CONTROLLER CCM 8-SOIC
IR1150SPBFCT-ND - IC PFC CONTROLLER CCM 8-SOIC
IR1150SPBFTR-ND - IC PFC CONTROLLER CCM 8-SOIC
IR1150SCT-ND - IC PFC CONTROLLER CCM 8-SOIC
3.3 Design Tips for Optimized Operation
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Minimize gate drive current loop - Ground pin of IC, current sense resistor, and
source of power switch should be as close to a single node as practically possible. A
star point connection, although not always practical in real world pcb layout, is
optimum.
single connection point
minimize this loop area
Figure 10 – Connection of Power Switch Source, Current Sense Resistor, and IC Ground
?
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The IRAC1150-D2 provides a robust 1.5A peak gate current. Optimization of gate
drive resistors is required to achieve optimum performance in terms of system noise,
EMI and efficiency. Match the drive circuit to the power switch and system
requirements – e.g. the larger IRAC1150-300W Demo Board employs an
IRFP27N60K power switch. The turn-on resistance is 8.9 ? and the turn off resistance
is 2.7 ? . This offers a good compromise between switching losses and EMI. The
gate resistors selected will depend upon the desired system level performance, the
power switch selection, the boost diode selection, etc. Please refer to application
notes available on the International Rectifier website which address gate drive design
and optimization.
An additional feature of the IRAC1150-D2 is the OVP/EN function, (pin 5), which is
shown in the circuit of Figure 7 as not connected. This pin can be brought out into
the circuit in order to initiate “sleep mode” feature of the IR1150S control IC.
Rev. 2.0
7/6/2005
International Rectifier
Page 12 of 12
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