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| 型号： | IRAC5001-HS100A |
| 厂商： | International Rectifier |
| 文件页数： | 3/12页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL ORING DEMO BOARD/IR5001 |
| 标准包装： | 1 |
| 其它名称： | *IRAC5001-HS100A |
IRAC5001-HS100A ORing Demo Board
CIRCUIT OPERATION :
The diagram in Figure 2 shows the test setup to evaluate the functionality of this
demo board in each of 12Volt power supply output connected to the system bus
load.
The power load can be a single high power E-load (~1kW) or composed of
several medium power E-loads ( 3 x 300W ) connected in parallel. At least 2
units of high power converter - each capable of sourcing 100Amp is required to
check the OR-ing functionality. Each power supply should have an output
voltage setting of about 12V ( +/- 0.01 V ) to simulate a near balanced current
sharing condition, and each output is link to the bus by one demo board-
individually powered by a floating 12Volt DC supply ( bias voltage) through
connector CON5. This connector route the positive bias voltage to the IC’s pin 7
(Vcc : < 13.9Vmax) and the negative bias to the output rail connector (Con1) of
the power converter. This is necessary to drive the gates of 4 IRF6609 OR-FETs
in parallel linking the highside (or positive output rail) to the positive of the bus.
The negative rails of all power converters are all connected together to the
negative rail of the bus.
Since this is a high current test setup, extra care should be observed
in proper connections on the board to avoid unnecessary contact
resistance which may further add heat to the board itself.
As a general design practice in choosing the appropriate mosfets, they must
have low Rds on and the Vsd generated should be at least ~50mV when the OR-
FET is “ON”.
FETCHK FEATURE
Ensure the test setup is correct and both power converters and OR-ing boards
are in good condition before starting-up. For safe initial test, it is recommended
to power up the OR-ing boards first with system load preset to less than 10Amps
as startup load before doing the full load test. The thermal performance should
be acceptable at room temperature testing even if the OR-ing board has no
heatsink but do not press one or both FETSW for too long . This test will force
the circuit to conduct the total load current through the body diodes of the OR-
FET which will increase the heat dissipation at a very fast rate; thus extra
precaution must be observed during this FETCHK test.
MODEL : IRAC5001-HS100A ORing DEMO BOARD
DOCUMENT Name : IRAC5001-HS100A_USERGUIDE_Rev1.3
Documented by : Israel Serrano, IR Singapore Design Center
DATE : 8/3/2004
PN : 1950-1003_Rev_1.3
Page 3 of 12
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
http://www.irf.com / Data and specifications subject to change without notice.
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