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参数资料
| 型号： | IRDC3621 |
| 厂商： | International Rectifier |
| 文件页数： | 5/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL DUAL SYNC BUCK CTRLR |
| 产品变化通告： | (EP) Parts Discontinuation 25/May/2012 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.8V，2.5V |
| 电流 - 输出： | 10A，10A |
| 输入电压： | 5.5 ~ 14.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 400kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | IR3621 |
| 产品目录页面： | 1383 (CN2011-ZH PDF) |
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IR3621 & (PbF)
PIN DESCRIPTIONS
TSSOP
1
2
MLPQ
29
30
PIN SYMBOL
PGood
Vcc
PIN DESCRIPTION
Power Good pin. Low when any of the outputs fall 10% below the set voltages.
Supply voltage for the internal blocks of the IC. The Vcc slew rate should be
<0.1V/us.
3
4
5,23
6,22
31
1
2,22
3,21
V OUT3
Rt
V SEN2 , V SEN1
Fb2,Fb1
Output of the internal LDO. Connect a 1.0uF capacitor from this pin to ground.
Connecting a resistor from this pin to ground sets the oscillator frequency.
Sense pins for OVP and PGood. For current share tie these pins together.
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is con-
nected to a resistor divider to set the output voltage and Fb2 is connected to
programming resistor to achieve current sharing. In independent 2-channel mode,
these pins work as feedback inputs for each channel.
7,21
4,20
Comp2, Comp1 Compensation pins for the error amplifiers.
8
20
5
19
SS2 / SD
SS1 / SD
These pins provide user programmable soft-start function for each outputs.
Connect external capacitors from these pins to ground to set the start up time
for each output. These outputs can be shutdown independently by pulling the
respective pins below 0.3V. During shutdown both MOSFETs will be turned off.
For current share mode SS2 must be floating.
9,19
6,18
OCSet2,OCSet1 A resistor from these pins to switching point will set current limit threshold.
10,18
7,17
VcH2, VcH1
Supply voltage for the high side output drivers. These are connected to voltages
that must be typically 6V higher than their bus voltages. A 0.1 μ F high fre-
quency capacitor must be connected from these pins to PGND to provide peak
drive current capability.
11,17
8,16
HDrv2, HDrv1
Output drivers for the high side power MOSFETs. Note3
12,16
10,14
PGnd2, PGnd1 These pins serve as the separate grounds for MOSFET drivers and should be
connected to the system’s ground plane.
13,15
14
24
25
11,13
12
23
24
LDrv2, LDrv1
V CL
Sync
Hiccup
Output drivers for the synchronous power MOSFETs.
Supply voltage for the low side output drivers.
The internal oscillator can be synchronized to an external clock via this pin.
When pulled High, it puts the device current limit into a hiccup mode. When
pulled Low, the output latches off, after an overcurrent event.
26
26
V P2
Non-inverting input to the second error amplifier. In the current sharing mode, it
is connected to the programming resistor to achieve current sharing. In inde-
pendent 2-channel mode it is connected to V REF pin when Fb2 is connected to
27
28
27
28
9,15,25.32
V REF
Gnd
N/C
the resistor divider to set the output voltage.
Reference Voltage. The drive capability of this pin is about 2 μ A.
Analog ground for internal reference and control circuitry.
No Connect
Note3: The negative voltage at these pins may cause instability for the gate drive circuits. To prevent this, a low
forward voltage drop diode (Schottky) is required between these pins and power ground.
www.irf.com
5
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