参数资料
型号: IRDC3810
厂商: International Rectifier
文件页数: 16/21页
文件大小: 0K
描述: BOARD EVAL SYNC BUCK CONVERTER
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 1
系列: *
PD-60344
IR3810MPbF
The R DS(on)
Programming the Current-Limit
The Current-Limit threshold can be set by
connecting a resistor (R SET ) from drain of the
low-side MOSFET to the OCSet pin. The
resistor can be calculated by using equation (3).
has a positive temperature
coefficient and it should be considered for the
worse case operation. This resistor must be
placed close to the module, place a small
ceramic capacitor from this pin to power ground
(PGnd) for noise rejection purposes.
Layout Consideration
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with less than expected results.
Start to place the power components, making all
the connection in the top layer with wide, copper
filled areas.
The inductor, output capacitor and the IR3810
should be as close to each other as possible.
This helps to reduce the EMI radiated by the
I SET = I L(critical ) =
R OCSet ? I OCSet
R DS(on)
- -(3)
power traces due to the high switching currents
through them. Place the input capacitor directly to
the Vin pin of IR3810. To reduce the ESR replace
the single input capacitor with two parallel units.
The feedback part of the system should be kept
I SET = (I o ? 1 . 5 ) +
Δ i = ( V in - V o ) ?
R DS(on) = 6.9m ? ? υ = 6.9m ? ? 1 .5 = 10.35m ?
where :
υ : Temperatur e Dependency
Note : Use 9.3 m ? for low - side MOSFET
if 5V is used for V cc
Δ i
2
where :
I o : Max Output Current
Δ i : I nductor ripple current
V o
V in ? L ? F s
I SET = (12A * 1.5) + 1.7A = 19.7A
R OCSet = R 7 = 10.2K ?
11/04/08
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vcc and Vc should be close to their
respective pins. It is important to place the
feedback components including feedback
resistors and compensation components close to
Fb and Comp pins.
In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are
referenced. The goal is to localize the high
current path to a separate loop that does not
interfere with the more sensitive analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
The Power QFN is a thermally enhanced
package. Based on thermal performance it is
recommended to use at least a 4-layers PCB. To
effectively remove heat from the device the
exposed pad should be connected to the ground
plane using vias.
16
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