参数资料
型号: IRDC3831
厂商: International Rectifier
文件页数: 16/31页
文件大小: 0K
描述: BOARD EVAL SYNC BUCK CONVERTER
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 1
系列: SupIRBuck™
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 0.75V
电流 - 输出: 8A
输入电压: 12V
稳压器拓扑结构: 降压
频率 - 开关: 400kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: IR3831
IR3831MPbF
? .......... .......... .......... .... (8)
R 9 = R 8 ? ?
Application Information
Design Example:
The following example is a typical application for
IR3831. The application circuit is shown on page
22.
V in = 12 V ( 13.2V max)
V o = 0.75 V
I o = 8 A
Δ V o ≤ 22.5mV
F s = 400 kHz
Enabling the IR3831
As explained earlier, the precise threshold of
the Enable lends itself well to implementation of
a UVLO for the Bus Voltage.
V in
When an external resistor divider is connected to
the output as shown in figure 10.
Equation (5) can be rewritten as:
? V p ?
? ?
? V o ? V p ?
For low voltage applications, such as this
design, it is often advisable to eliminate the bias
resistor R9 from Fb to ground. For the calculated
value of R8 see feedback compensation section.
IR3831
Enable
R 1
R 2
Fig. 10. Typical application of the IR3831 for
programming the output voltage
Further, the tracking reference Vp may be itself
derived from some master reference by means
of a resistive divider as shown in Fig. 9. This is
For a typical Enable threshold of V EN = 1.2 V
common in active bus termination circuits such
as Voltage Tracking Termination (VTT) where
V in (min) *
R 2
R 1 + R 2
= V EN = 1.2 .......... (5)
the tracking reference Vp may be obtained as
half of the master reference VDDQ which forms
the input to one or more memory banks.
R 2 = R 1
V EN
V o = V p ? ? ? 1 + 8 ? ? .......... .......... .......... .....(7)
.......... (6)
V in( min ) ? V EN
For a V in (min) =10.2V, R 1 =4.99K and R 2 =750 ohm
is a good choice.
Programming the frequency
For F s = 400 kHz, select R t = 35.7 k ? , using
Table. 1.
Output Voltage Programming
Output voltage is programmed by the tracking
reference voltage at Vp and external voltage
divider. The divider is ratioed such that the
voltage at the Fb pin is equal to the voltage at the
Vp pin pin when the output is at its desired value.
The output voltage is defined by using the
following equation:
? R ?
? R 9 ?
11/05/10
In this design,
VDDQ =1.5V
R p1 = R p2 =1.5 k ?
Vp =0.75V
Soft-Start Programming
The soft-start timing can be programmed by
selecting the soft-start capacitance value. From
(1), for a desired start-up time of the converter,
the soft start capacitor can be calculated by
using:
C SS ( μ F ) = T start ( ms ) × 0.02857 .......... (9)
Where T start is the desired start-up time (ms).
For tracking applications the output is generally
required to track Vp even at start-up. Hence, it is
necessary to ensure that the SS pin is already
up to 3 V before the tracking reference signal is
applied to the Vp pin. This can be done by
choosing a small value for the soft-start
capacitor to ensure that the voltage at the SS pin
rises to 3 V quickly. A 0.022 uF capacitor is
chosen for this purpose.
16
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