参数资料
型号: IRDC3865
厂商: International Rectifier
文件页数: 17/22页
文件大小: 0K
描述: BOARD EVAL SUPIRBUCK IR3865
产品培训模块: SupIRBuck? Family and POL Design Tools Overview
标准包装: 1
系列: SupIRBuck™
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.05V
电流 - 输出: 10A
输入电压: 7 ~ 16 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: IR3865
IR3865MPBF
STABILITY CONSIDERATIONS
Constant-on-time control is a fast , ripple based
control scheme. Unstable operation can occur
if certain conditions are not met. The system
instability is usually caused by:
? Switching noise coupled to FB input:
This causes the PWM comparator to trigger
prematurely after the 400ns minimum on-time
for lower MOSFET. It will result in double or
multiple pulses every switching cycle instead
of the expected single pulse. Double pulsing
can causes higher output voltage ripple, but in
most application it will not affect operation.
This can usually be prevented by careful
layout of the ground plane and the FB sensing
trace.
? Steady state ripple on FB pin being too small:
The PWM comparator in IR3865 requires
minimum 7mVp-p ripple voltage to operate
stably. Not enough ripple will result in similar
double pulsing issue described above. Solving
this may require using output capacitors with
higher ESR.
? ESR loop instability:
The stability criteria of constant on-time is:
ESR*Cout>Ton/2. If ESR is too small that this
criteria is violated then sub-harmonic
oscillation will occur. This is similar to the
instability problem of peak-current-mode
control with D>0.5. Increasing ESR is the
most effective way to stabilize the system, but
the tradeoff is the larger output voltage ripple.
8/8/2012 Rev3.1
? System with all ceramic output capacitors:
For applications with all ceramic output
capacitors, the ESR is usually too small to
meet the stability criteria. In these
applications, external slope compensation is
necessary to make the loop stable. The ramp
injection circuit, composed of R6, C13, and
C14, shown in Figure 7 is required. The
inductor current ripple sensed by R6 and C13
is AC coupled to the FB pin through C14. C14
is usually chosen between 1 to 10nF, and
C13 between 10 to 100nF. R6 should then be
chosen such that L/DCR = C13*R6.
? System with electrolytic output capacitors:
The electrolytic capacitors usually have higher
ESL than POSCAPs and ceramic capacitors.
The effect of high ESL is undesirable spike on
the FB node causing false trigger of a new
switching cycle. The ESR of electrolytic
capacitors also comes in a wide range, such
that in some cases we need to filter out the
spikes caused by its high ESL while providing
injected ripple to compensate for low ESR.
The circuit composed of R13, C24, and C14
shown in Figure 7 acts as a filter and a ramp
generator. As an example, if two Nichicon
PW-series, 1000uF, 16V through hole
electrolytic capacitor are used for 12Vin,
5Vout, and 300kHz switching; the suggested
compensation values are: R13 = 20 Ω, C24 =
1uF, and C14 = 1000pF. Equations for
determining these values have not been
established. If electrolytic or other high ESL
capacitors are required, IR's application team
will gladly assist you to determine an optimal
compensation scheme.
17
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