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参数资料
| 型号： | IRDC3871 |
| 厂商： | International Rectifier |
| 文件页数： | 11/21页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR IRDC3871 |
| 标准包装： | 1 |
| 系列： | SupIRBuck™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.05V |
| 电流 - 输出： | 8A |
| 输入电压： | 12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | IR3871 |
IR3871MPBF
CIRCUIT DESCRIPTION
PWM COMPARATOR
The PWM comparator initiates a SET signal
(PWM pulse) when the FB pin falls below the
reference (Vref) or the soft start (SS) voltage.
ON-TIME GENERATOR
The PWM on-time duration is programmed with
an external resistor (R FF ) from the input supply
(VIN) to the FF pin. The simplified calculation for
R FF is shown in equation 1. The FF pin is held to
an internal reference after EN goes HIGH. A copy
of the current in R FF charges a timing capacitor,
which sets the on-time duration, as shown in
equation 2.
PGOOD
The PGOOD pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation. The PGOOD logic monitors
EN_DELAY, SS_DELAY, and under/over voltage
fault signals. PGOOD is released only when
EN_DELAY and SS_DELAY = HIGH and output
voltage is within the OV and UV thresholds.
PRE-BIAS STARTUP
IR3871 is able to start up into pre-charged output,
which prevents oscillation and disturbances of the
output voltage.
R FF ?
T ON ?
V OUT
1 V ? 20 pF ? F SW
R FF ? 1 V ? 20 pF
V IN
(1)
(2)
With constant on-time control, the output voltage
is compared with the soft start voltage (SS) or
Vref, depending on which one is lower, and will
not start switching unless the output voltage drops
below the reference. This scheme prevents
discharge of a pre-biased output voltage.
CONTROL LOGIC
The control logic monitors input power sources,
sequences the converter through the soft-start
and protective modes, and initiates an internal
RUN signal when all conditions are met.
SHUTDOWN
The IR3871 will shutdown if VCC is below its
UVLO limit. The IR3871 can be shutdown by
pulling the EN pin below its lower threshold.
Alternatively, the output can be shutdown by
pulling the soft start pin below 0.3V.
VCC and 3VCBP pins are continuously monitored,
and the IR3871 will be disabled if the voltage of
either pin drops below the falling thresholds.
EN_DELAY will become HIGH when VCC and
3VCBP are in the normal operating range and the
EN pin = HIGH.
SOFT START
With EN = HIGH, an internal 10μA current source
charges the external capacitor (C SS ) on the SS pin
to set the output voltage slew rate during the soft
start interval. The soft start time (t SS ) can be
calculated from equation 3.
t SS ?
C SS ? 0.5 V
10 ? A
(3)
The feedback voltage tracks the SS pin until SS
reaches the 0.5V reference voltage (Vref), then
feedback is regulated to Vref. C SS will continue to
be charged, and when SS pin reaches V SS (see
Figure 18. Normal Startup
Electrical Specification ), SS_DELAY goes HIGH.
With EN_DELAY = LOW, the capacitor voltage
and SS pin is held to the FB pin voltage. A normal
startup sequence is shown in Figure 18.
11
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| IRDC3876 | 制造商:International Rectifier 功能描述:9999V 999.000A POL IC - Rail/Tube 制造商:International Rectifier 功能描述:BOARD EVAL FOR IR3876 |
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