参数资料
型号: IRDCIP2005C-1
厂商: International Rectifier
文件页数: 12/15页
文件大小: 0K
描述: BOARD DEMO SYNC BUCK CONVETER
标准包装: 1
系列: *
i P2005CPbF
PD-60360
C1x
P GND
V IN
C6x
P GND
V IN
C3
P GND
V IN
C2
P GND
V IN
C1
P GND
V IN
L1
U1
V IN
1
N/C
8
N/C
V IN
V IN
V IN
7
V SW
V SW
2
ENABLE
6
P GND
P GND
P GND
PWM
P GND
5
C4
C5
C6
3
Top Component Layer
V DD
4
Bottom Component Layer
Figure 14 Top & Bottom Component and Via Placement (Topside, Transparent view down)
PCB Layout Guidelines
The following guidelines are recommended to reduce the parasitic values and optimize overall
performance.
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All pads on the iP2005C footprint design need to be Solder-mask defined (see Figure 13).
Also refer to International Rectifier application notes AN1028 and AN1029 for further footprint
design guidance.
Place as many vias around the Power pads (V IN , V SW , and P GND ) for both electrical and optimal
thermal performance.
A minimum of six 10μF, X5R, 16V ceramic capacitors per iP2005C are needed for greater
than 30A operation at 1MHz switching frequency. This will result in the lowest loss due to
input capacitor ESR.
Placement of the ceramic input capacitors is critical to optimize switching performance. In
cases where there is a heatsink on the case of iP2005C, place all six ceramic capacitors right
underneath the iP2005C footprint (see Figure Bottom Component Layer). In cases where
there is no heatsink, C1 and C6 on the bottom layer may be moved to the C1x and C6x
locations (respectively) on the top component layer (see Figure Top Component Layer). In
both cases, C2 – C5 need to be placed right underneath the iP2005C PCB footprint.
Dedicate at least two layers to PGND.
Duplicate the Power Nodes on multiple layers (refer to AN1029).
www.irf.com
04/09/2009
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