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参数资料
| 型号： | IRMD2336DJ |
| 厂商： | International Rectifier |
| 文件页数： | 31/49页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRIVER |
| 标准包装： | 1 |
| 系列： | * |
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IRS2336x(D) Family
DC+ BUS
Q1
ON
I U
V S1
Q2
D2
OFF
DC- BUS
Figure 26: Q1 conducting
Figure 27: D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 28 and 29), and Q4
IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V S2 ,
swings from the positive DC bus voltage to the negative DC bus voltage.
Figure 28: D3 conducting
Figure 29: Q4 conducting
However, in a real inverter circuit, the V S voltage swing does not stop at the level of the negative DC bus, rather it
swings below the level of the negative DC bus. This undershoot voltage is called “negative V S transient”.
The circuit shown in Figure 30 depicts one leg of the three phase inverter; Figures 31 and 32 show a simplified
illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from
the die bonding to the PCB tracks are lumped together in L C and L E for each IGBT. When the high-side switch is on,
V S1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the
circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling
diode due to the inductive load connected to V S1 (the load is not shown in these figures). This current flows from the
DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between V S1 and the
DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the V S pin).
www.irf.com
31
? 2009 International Rectifier
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