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参数资料
| 型号： | IRPLCFL8U |
| 厂商： | International Rectifier |
| 文件页数： | 15/27页 |
| 文件大小： | 0K |
| 描述： | KIT DES FLUOR BALLAST IRS2530D |
| 标准包装： | 1 |
| 主要目的： | 照明，镇流器控制 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | IRS2530D |
| 主要属性： | 32W，调光，120 VAC |
| 次要属性： | 预热，自动预热，电压不足保护 |
| 已供物品： | 板，CD |
| 相关产品： | IRS2530DSPBF-ND - IC BALLAST CTRL DIM 600V 8-SOIC IRS2530DSTRPBFDKR-ND - IC DIMMING BALLAST CTRL 8-SOIC IRS2530DSTRPBFCT-ND - IC DIMMING BALLAST CTRL 8-SOIC IRS2530DSTRPBFTR-ND - IC DIMMING BALLAST CTRL 8-SOIC IRS2530DPBF-ND - IC CTRL BALLAST DIMMING 8-DIP |
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7. Fault Conditions
In case of fault conditions such as open filaments, failure to strike, or lamp removal, the
IRS2530D will go into Fault Mode. In this mode, the internal fault latch is set, HO is off, LO
is open circuit, and the IRS2530D consumes an ultra-low micro-power current. The
IRS2530D can be reset with a lamp exchange (as detected by the LO pin) or a recycling of
VCC below and back above the UVLO thresholds.
Failure to Strike
At initial turn-on of the ballast, the frequency will ramp down from f MAX toward the
resonance frequency. When the lamp fails to strike, the VCO voltage continues to
increase and the frequency continues to decrease until the VCO voltage exceeds
VVCOFLT+ (4.0V, typical), and the IRS2530D enters Fault Mode and shuts down
(Figure 7.1). It should be noted that in case of failure to strike, the system will operate in
capacitive side of resonance, but only for short period of time.
Figure 7.1: Lamp non-strike: CH1 is the VCO voltage, CH4 is the voltage across lamp
AC Mains Interrupt / Brown-Out Conditions
This protection relies on the non-ZVS circuit of IRS2530D, enabled in the Dim Mode.
During an AC mains interrupt or brown-out condition, the DC bus can decrease and
cause the system to operate too close to, or, on [the] capacitive side of resonance. The
result is non-ZVS switching that causes high peak currents to flow in the half-bridge
MOSFETs that can damage or destroy them.
To protect against this, the IRS2530D will detect non-ZVS by measuring the VS voltage
at each rising edge of LO. If the voltage is greater than VZVSTH (4.5V, typical), the IC
will reduce the voltage at VCO pin, and thus increase the frequency until ZVS is
reached again (Figure 7.2).
www.irf.com
RD0803
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