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| 型号： | IRPP3637-06A |
| 厂商： | International Rectifier |
| 文件页数： | 3/14页 |
| 文件大小： | 0K |
| 描述： | BOARD REF DESIGN POWIR+ |
| 标准包装： | 1 |
| 系列： | * |
Total FET losses:
Start-Up Procedure
The 5V input power is connected
between terminals J1 and J2 and the
1.25V, 6A output power is obtained
through terminals J3 and J4.
The V CC and V C pins are the low side
driver and high side driver power input
pins respectively. The V CC pin also
includes the housekeeping power of the
PWM controller. An under-voltage
lockout (UVLO) feature is associated
with each of these pins, which is set to
4.2V for V CC and 3.3V for V C . A charge
pump circuit comprised of C13, D1, and
C14 applies approximately twice the
input voltage to the V C pin to allow fast
driving capability, hence reducing the
switching losses of the control FET
(Q1).
Upon application of the input power, the
output starts ramping up to regulation
within 4ms. The ramping time can be
adjusted through the soft start capacitor
C5. The output voltage of the
synchronous buck regulator is set to
1.25V using the internal 0.8V reference
voltage.
The following equations are used to
calculate the MOSFET power loss.
Refer to the IRF8910PBF datasheet to
select the parametric values of the
power loss equations terms.
Eq (4):
P FET _ total = P Q 1 + P Q 2 + P td
Where,
I Q1rms and I Q2rms are the rms currents for
control and sync FETs respectively, in
Amps
I O is the output load current in Amps
R D is the R DSON in ohms of the FETs and
R Dn is the normalized R DSON factor vs
temperature extracted from the
IRF8910PBF datasheet.
Q SW is the FET switch charge in nC
V IN is the input voltage of the sync buck
converter
Q g is the total gate charge in nC.
V dd is the FET drive voltage, which is
4.5V.
I g is the drive current which is 0.25A.
Q OSS is the FET output charge in nC.
Q rr is the sync FET internal body diode
reverse recovery charge in nC
V SD is the sync FET internal body diode
forward voltage drop in volts. F SW is the
switching frequency of the sync buck
converter in hertz.
td is the dead time caused by the PWM
controller IC in seconds. This parameter
is specified in IR3637ASPBF datasheet.
For design calculations related to
programming the output voltage and the
soft start time, selection of input/output
capacitors and output inductor and
P Q 1 = I Q 1 rms 2 . R DQ 1 . R Dn + ( I o .
Control FET Losses:
Eq (1):
Q sw 1
I g 1
. V in + Q gQ 1 . V dd + Q ossQ 1 . V in ). F SW
control loop compensation, refer to the
guidelines outlined in the IR3637ASPBF
PWM controller datasheet.
IR's online design tool POWIR + should
? Q ossQ 2
P Q 2 = I Q 2 rms 2 . R DQ 2 . R Dn + ?
. V in + Q gQ 2 . V dd + Q rrQ 2 . V in ? . F SW
?
?
Synchronous FET Losses:
Eq (2):
? 2 ?
Deadtime losses:
Eq (3):
P td = V SD . I o . t d . F sw
?
be used to customize a design for
applications outside the standard 4.5V
to 5.5V input range and 1.25V output,
and for varied design goal objectives.
www.irf.com
RD-0604
3
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