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参数资料
| 型号： | IRPT4052 |
| 文件页数： | 11/12页 |
| 文件大小： | 174K |
| 代理商： | IRPT4052 |
page 11
IRPT 4052
Functional Information
Capacitor Precharge
When the input line voltage is first switched on, the charging
current of the DC bus capacitors is limited by a 100 Ohm pre-
charge resistor. When the bus capacitor has charged to
approximately 85% of the peak line voltage, the capacitor pre-
charge control circuit energizes the relay K1, bypassing the
100y pre-charge resistor, so long as the line voltage exceeds
300V rms and all three input phase voltages are present.
The relay feedback signal, K1FB is the voltage across the re-
lay coil. This is 15V high when the relay is energized, and low
when the relay is de-energized. At start-up, the input PWM sig-
nals should be inhibited externally until K1FB becomes high,
since if the inverter is operated before the pre-charge resistor is
bypassed, this resistor will be overloaded. The relay will drop
out during operation if the DC bus voltage falls to less than 82%
of the peak line voltage; if one or more input line voltages is
lost; or if the input voltage falls below 300V. K1FB then be-
comes low and the PWM input signals should be inhibited
externally to avoid overloading the pre-charge resistor.
The BUS RIPPLE feedback signal is high when the relay is
de-energized, and low when it is energized. If one of the input
phases is lost, the relay drops out and the BUS RIPPLE signal
oscillates from high to low at line frequency.
The relay can be energized, if required, during single-phase
operation by pulling down the SFT CHG terminal via an external
open-collector transistor. The pull-down current is 2mA.
Discharging the Bus Capacitors
When the input power is switched off, the “top” bus capacitor
is discharged by a 10k resistor.
The “lower” bus capacitor is discharged by a 10k resistor until
its voltage reaches approximately 80V. Thereafter, discharge of
the “lower” capacitor is via a 110k resistor.
Bootstrap Supplies for the Gate Drive Circuits
The gate drive circuits for the upper IGBTs are powered from
floating bootstrap capacitors. Each bootstrap capacitor is charged
via the corresponding lower IGBT when this is switched on.
Prior to initial application of the PWM input signals at start-up,
the bootstrap capacitors are uncharged. Thus, an upper IGBT
will not be turned on until after the corresponding lower IGBT
has first been turned on to charge the bootstrap capacitor for the
upper IGBT. The minimum initial conduction period of each
lower IGBT at start-up should be about 50μsec, to allow suffi-
cient time for initial charging of the bootstrap capacitors. In
normal operation, the bootstrap capacitor maintains adequate
gate drive voltage for a period of 20 milliseconds. The maximum
duration of the PWM input pulses (1N1, 1N3 and 1N5) should
not exceed this period.
PWM Input Signals
PWM input signals must be 15V positive logic. They must
source 10mA into the opto-isolators of the IGBT gate driver cir-
cuits. When inhibited by the internal PWM gate during power
up, power down and fault conditions, each PWM input signal
becomes loaded by a 720 Ohm resistor. Maximum rise and fall
times of the PWM input signals should be 150 nsecs. Minimum
dead time between outgoing and incoming PWM signals to the
IGBTs in a given inverter leg should be 2.5μsecs. This is neces-
sary to avoid inverter shoot-through. The minimum duration of
any PWM input pulse should be 1μsec. Typical propagation de-
lay between the PWM input and drive output at the gate of the
IGBT is 300ns.
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